The OV5640 device tree overlay incorrectly defined an I2C switch
instead of an I2C mux. According to the DT bindings, the correct
terminology and node definition should use "i2c-mux" instead of
"i2c-switch". Hence, update the same to avoid dtbs_check warnings.
Fixes: 635ed97151 ("arm64: dts: ti: k3-am62x: Add overlays for OV5640")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jai Luthra <jai.luthra@linux.dev>
Link: https://lore.kernel.org/r/20250415111328.3847502-8-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The IMX219 device tree overlay incorrectly defined an I2C switch
instead of an I2C mux. According to the DT bindings, the correct
terminology and node definition should use "i2c-mux" instead of
"i2c-switch". Hence, update the same to avoid dtbs_check warnings.
Fixes: 4111db03dc ("arm64: dts: ti: k3-am62x: Add overlay for IMX219")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jai Luthra <jai.luthra@linux.dev>
Link: https://lore.kernel.org/r/20250415111328.3847502-7-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The IMX219 sensor device tree bindings do not include a clock-names
property. Remove the incorrectly added clock-names entry to avoid
dtbs_check warnings.
Fixes: 4111db03dc ("arm64: dts: ti: k3-am62x: Add overlay for IMX219")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jai Luthra <jai.luthra@linux.dev>
Link: https://lore.kernel.org/r/20250415111328.3847502-6-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The device tree overlay for the IMX219 sensor requires three voltage
supplies to be defined: VANA (analog), VDIG (digital core), and VDDL
(digital I/O). Add the corresponding voltage supply definitions to
avoid dtbs_check warnings.
Fixes: f767eb9180 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250415111328.3847502-5-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The IMX219 sensor device tree bindings do not include a clock-names
property. Remove the incorrectly added clock-names entry to avoid
dtbs_check warnings.
Fixes: f767eb9180 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jai Luthra <jai.luthra@linux.dev>
Link: https://lore.kernel.org/r/20250415111328.3847502-4-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Update the vin-supply of the TLV71033 regulator from LM5141 (vsys_3v3)
to LM61460 (vsys_5v0) to match the schematics. Add a fixed regulator
node for the LM61460 5V supply to support this change.
AM68-SK schematics: https://www.ti.com/lit/zip/sprr463
Fixes: a266c180b3 ("arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250415111328.3847502-3-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add device tree nodes for two power regulators on the J721E SK board.
vsys_5v0: A fixed regulator representing the 5V supply output from the
LM61460 and vdd_sd_dv: A GPIO-controlled TLV71033 regulator.
J721E-SK schematics: https://www.ti.com/lit/zip/sprr438
Fixes: 1bfda92a3a ("arm64: dts: ti: Add support for J721E SK")
Cc: stable@vger.kernel.org
Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250415111328.3847502-2-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Since serdes0 and serdes1 are now enabled by default within the SoC
file, it is no longer necessary to enable them in the board file.
Hence, remove the redundant 'status = "okay"' within the serdes0 and
serdes1 device-tree nodes.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250417123246.2733923-5-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Since serdes0 and serdes1 are the child nodes of serdes_wiz0 and
serdes_wiz1 respectively, and, given that serdes_wiz0 and serdes_wiz1
are already disabled, it is not necessary to disable serdes0 and serdes1.
Moreover, having serdes_wiz0/serdes_wiz1 enabled and serdes0/serdes1
disabled is not a working configuration.
Hence, remove 'status = "disabled"' from the serdes0 and serdes1 nodes.
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250417123246.2733923-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Since "serdes0" and "serdes1" which are the sub-nodes of "serdes_wiz0"
and "serdes_wiz1" respectively, have been disabled in the SoC file already,
and, given that these sub-nodes will only be enabled in a board file if the
board utilizes any of the SERDES instances and the peripherals bound to
them, we end up in a situation where the board file doesn't explicitly
disable "serdes_wiz0" and "serdes_wiz1". As a consequence of this, the
following errors show up when booting Linux:
wiz bus@f0000:phy@f000000: probe with driver wiz failed with error -12
...
wiz bus@f0000:phy@f010000: probe with driver wiz failed with error -12
To not only fix the above, but also, in order to follow the convention of
disabling device-tree nodes in the SoC file and enabling them in the board
files for those boards which require them, disable "serdes_wiz0" and
"serdes_wiz1" device-tree nodes.
Fixes: 628e0a0118 ("arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support")
Cc: stable@vger.kernel.org
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250417123246.2733923-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree
nodes in the SoC file, enable them in the board file. The motivation for
this change is that of following the existing convention of disabling
nodes in the SoC file and only enabling the required ones in the board
file.
Fixes: 485705df5d ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM")
Cc: stable@vger.kernel.org
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250417123246.2733923-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The "pinctrl-names" property is not required since it doesn't have an
associated pinctrl configuration. Hence, drop it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250411061425.640718-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.
Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-3-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.
Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.
Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
J722S EVM has four RPi camera connectors and dual MIPI Samtec CSI
connectors which bring out the 4 x CSI2RX instances and the I2C camera
control interfaces. Add the nodes for PCA9543 I2C switch and enable them.
J722S EVM schematics: https://www.ti.com/lit/pdf/sprujb5
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
J722S has 4 CSI2RX receiver instances with external DPHY. The first CSI2RX
instance node is derived from the AM62P common dtsi, Add the nodes for the
subsequent three instances and keep them disabled.
TRM (12.6 Camera Peripherals): https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
J722S has a dedicated CSI BCDMA instance which is slightly different
from AM62P in TX channel support, add the overrides and additional
properties to support CSI BCDMA on J722S.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working pinctrl configurations for GPIOs within the device tree.
This is what happens:
(1) During startup the pinctrl settings are applied according to the
device tree. I.e. the pin is configured as output and with
pull-ups enabled.
(2) During startup a device driver requests a GPIO.
(3) pinctrl-single is applying the default GPIO setting according to
the pinctrl-single,gpio-range property.
This would work as expected if the pinctrl-single is only controlling
the function mux, but it also controls the input/output buffer enable,
the pull-up and pull-down settings etc (pinctrl-single,function-mask
covers the entire pad setting instead of just the mux field).
Remove the pinctrl-single,gpio-range property, so that no settings are
applied during a gpio_request() call.
Fixes: 5e5c50964e ("arm64: dts: ti: k3-j722s: Add gpio-ranges properties")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20250221091447.595199-2-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working pinctrl configurations for GPIOs within the device tree.
This is what happens:
(1) During startup the pinctrl settings are applied according to the
device tree. I.e. the pin is configured as output and with
pull-ups enabled.
(2) During startup a device driver requests a GPIO.
(3) pinctrl-single is applying the default GPIO setting according to
the pinctrl-single,gpio-range property.
This would work as expected if the pinctrl-single is only controlling
the function mux, but it also controls the input/output buffer enable,
the pull-up and pull-down settings etc (pinctrl-single,function-mask
covers the entire pad setting instead of just the mux field).
Remove the pinctrl-single,gpio-range property, so that no settings are
applied during a gpio_request() call.
Fixes: d72d73a44c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20250221091447.595199-1-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add a device tree overlay for SPI1 , UART3 and GPIO1 on
X27 connector.
By default, not all interfaces on the X27 connector are accessible
due to being disabled or set to alternative pin mux configurations.
This overlay activates and configures these interfaces to support
connections with external devices.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Link: https://lore.kernel.org/r/20250128100356.462934-1-d.schultz@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Commit under Fixes added the 'idle-states' property for SERDES4 lane muxes
without defining the corresponding register offsets and masks for it in the
'mux-reg-masks' property within the 'serdes_ln_ctrl' node.
Fix this.
Fixes: 7287d423f1 ("arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux")
Cc: stable@vger.kernel.org
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250228053850.506028-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.
Move ramoops to lower region so the IPC fits to the correct address.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250131093531.1054924-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250131093531.1054924-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB devices. This requires that
the pin corresponding to the Type-A connector remains pulled up even after
the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup /
pulldown selection for the USB1_DRVBUS pin and set its Deep Sleep state to
PULL_UP.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250130062550.1554651-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In the same lines of commit 9e8560556f ("arm64: dts: ti:
k3-am62x-sk-common: Reserve 128MiB of global CMA"), reserve global CMA
pool for:
LCD Display: 16MiB, HDMI (1080p): 16MiB, GPU: 16MiB, CSI2 1 1080p
sensor: 32MiB with a 32MiB set for other peripherals and a 16MiB
buffer.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20250131173508.1338842-1-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-SK is connected to USB0 via
SERDES3, supporting USB DFU boot requires SERDES3 link associated with
USB0 to be functional at all stages of the USB DFU boot process. Thus,
add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250209081738.1874749-3-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-EVM is connected to USB0 via
SERDES3, supporting USB DFU boot requires SERDES3 link associated with
USB0 to be functional at all stages of the USB DFU boot process. Thus,
add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250209081738.1874749-2-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Similar to the TI K3-AM62x Soc commit ce27f7f9e3
("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0")
The devices in the wkup domain are capable of waking up the system from
suspend. We can configure the wkup domain devices in a generic way using
the ti-sysc interconnect target module driver like we have done with the
earlier TI SoCs.
As ti-sysc manages the SYSCONFIG related registers independent of the
child hardware device, the wake-up configuration is also set even if
wkup_uart0 is reserved by sysfw.
The wkup_uart0 device has interconnect target module register mapping like
dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP
block in the target module. The power domain and clock affects the whole
interconnect target module.
Note we change the functional clock name to follow the ti-sysc binding
and use "fck" instead of "fclk".
Also note that we need to disable the target module reset as noted by
Markus. Otherwise the sysfw using wkup_uart0 can get confused on some
devices leading to boot time issues such as mbox timeouts.
Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Kendall Willis <k-willis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20250212215248.746838-1-k-willis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds alias for SoC RTC so that it gets assigned rtc0. PMIC node is
assigned rtc1 so that PMIC RTC gets probed as rtc1. This makes it
consistent for testing rtcwake with other AM62 devices where rtc0
is SoC RTC.
Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
[k-willis@ti.com: Reworded commit message]
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Kendall Willis <k-willis@ti.com>
Link: https://lore.kernel.org/r/20250214232212.1158505-1-k-willis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
When used as boot device, OSPI flash hosts different boot
binaries and rootfs etc.
So Add partition details for images hosted on OSPI flash.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250215070059.1593489-1-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The simple-audio-card's microphone widget currently connects to the
headphone jack. Routing the microphone input to the microphone jack
allows for independent operation of the microphone and headphones.
This resolves the following boot-time kernel log message, which
indicated a conflict when the microphone and headphone functions were
not separated:
debugfs: File 'Headphone Jack' in directory 'dapm' already present!
Fixes: f5bf894c86 ("arm64: dts: ti: verdin-am62: dahlia: add sound card")
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Jai Luthra <jai.luthra@linux.dev>
Link: https://lore.kernel.org/r/20250217144643.178222-1-eichest@gmail.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Currently we get the warning:
"GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has
overlapping address"
As per TRM GICD is 64 KB. Fix it by correcting the size of GICD.
Cc: stable@vger.kernel.org
Fixes: 9cc161a450 ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
Link: https://lore.kernel.org/r/20250218052248.4734-1-j-keerthy@ti.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The USB0 instance of USB on AM62Px SoC can be used for USB DFU boot. This
requires USB0 to be enabled at all stages of the boot process. In order to
support USB DFU boot on AM62P5-SK, add the "bootph-all" property to USB0.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250122124223.1118789-3-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The USB0 instance of USB on AM62Ax SoC can be used for USB DFU boot. This
requires USB0 to be enabled at all stages of the boot process. In order to
support USB DFU boot on AM62A7-SK, add the "bootph-all" property to USB0.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250122124223.1118789-2-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
J722S SOC has two usb controllers USB0 and USB1. USB0 is brought out on
the EVM as a stacked USB connector which has one Type-A and one Type-C
port. These Type-A and Type-C ports are connected to MUX so only
one of them can be enabled at a time.
Commit under Fixes, tries to enable the USB0 instance of USB to
interface with the Type-C port via the USB hub, by configuring the
USB2.0_MUX_SEL to GPIO_ACTIVE_HIGH. But it is observed on J722S-EVM
that Type-A port is enabled instead of Type-C port.
Fix this by setting USB2.0_MUX_SEL to GPIO_ACTIVE_LOW to enable Type-C
port.
Fixes: 485705df5d ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20250116125726.2549489-1-h-salunke@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The j784s4-evm board dts now has the gpio hogs for MUX2 after integration
of audio support. Remove duplicate gpio-hogs from the overlay dtso to
prevent mux probe failures leading to can-phy3 deferred probe:
'gpio-mux mux-controller: probe with driver gpio-mux failed with error -16'
Fixes: 479112c9f5 ("arm64: dts: ti: k3-j784s4-evm: Enable analog audio support")
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Link: https://lore.kernel.org/r/20250110105753.223049-1-j-choudhary@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Enable mcu domain pinmux by default to be able to access mcu domain
peripherals from main domain.
This also makes it consistent with the rest of the k3 platforms where
mcu domain pinmux is enabled by default.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
Link: https://lore.kernel.org/r/20250120075442.181191-1-s-adivi@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Similar to the TI K3-AM62x SoC commit ce27f7f9e3
("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0"),
The devices in the wkup domain are capable of waking up the system from
suspend. We can configure the wkup domain devices in a generic way using
the ti-sysc interconnect target module driver like we have done with the
earlier TI SoCs.
As ti-sysc manages the SYSCONFIG related registers independent of the
child hardware device, the wake-up configuration is also set even if
wkup_uart0 is reserved by sysfw.
The wkup_uart0 device has interconnect target module register mapping like
dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP
block in the target module. The power domain and clock affects the whole
interconnect target module.
Note we change the functional clock name to follow the ti-sysc binding
and use "fck" instead of "fclk".
Also note that we need to disable the target module reset as noted by
Markus. Otherwise the sysfw using wkup_uart0 can get confused on some
devices leading to boot time issues such as mbox timeouts.
Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
[d-gole@ti.com: Reworded the entire commit message]
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241231-am62a-dt-ti-sysc-wkup-v1-1-a9b0d18a2649@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add support for TPS6522x PMIC family on wakeup I2C0 bus.
This device provides regulators (bucks and LDOs), along with
GPIOs, and monitors SOC's MCU error signal.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250102103814.102499-1-u-kumar1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
AM69 SK board has two stacked USB3 connectors:
1. USB3 (Stacked TypeA + TypeC)
2. USB3 TypeA Hub interfaced through TUSB8041.
The board uses SERDES0 Lane 3 for USB3 IP. So update the
SerDes lane info for PCIe and USB. Add the pin mux data
and enable USB 3.0 support with its respective SERDES settings.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20250108-am69sk-dt-usb-v3-1-bb4981534754@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The reset deassert time for the DP83TD510E is incorrectly set to
60000us, while the datasheet states that the minimum time required
after an hard reset is 30us (while 60ms is the time required for the
Power-On Reset after supply stabilization). The error probably arose
from the two timings being indicated by the same symbol (T2).
Lower the required time to 35us, aligning it to the value required for
the PHY to complete the reset AND to be able to accept the RMII master
clock. This saves ~60ms on boot if the MDIO driver is built-in.
Signed-off-by: Francesco Valla <francesco@valla.it>
Link: https://lore.kernel.org/r/20250105162630.243899-1-francesco@valla.it
Signed-off-by: Nishanth Menon <nm@ti.com>
SolidRun HummingBoard-T has two options for M.2 connector, supporting
either PCI-E or USB-3.1 Gen 1 - depending on configuration of a mux
on the serdes lane.
The required configurations in device-tree were modeled as overlays.
The USB-3.1 overlay uses /delete-property/ to unset a boolean property
on the usb controller limiting it to USB-2.0 by default.
Overlays can not delete a property from the base dtb, therefore this
overlay is at this time useless.
Convert both overlays into full dts by including the base board dts.
While the pcie overlay was functional, both are converted for a
consistent user experience when selecting between the two mutually
exclusive configurations.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Closes: https://lore.kernel.org/linux-devicetree/CAMuHMdXTgpTnJ9U7egC2XjFXXNZ5uiY1O+WxNd6LPJW5Rs5KTw@mail.gmail.com
Fixes: bbef42084c ("arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20250101-am64-hb-fix-overlay-v2-1-78143f5da28c@solid-run.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in
Endpoint mode of operation. PCIE1 on AM68-SK-Base-Board supports x2 Lane
operation unlike its counterpart on J721S2-EVM which supports x1 Lane.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint
mode of operation. Additionally, in order to support both PCIE0 and PCIE1
in Endpoint Mode of operation, enable applying device-tree overlays on
"k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in
Endpoint mode to be applied on the aforementioned DTB.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The list of "dtbs" should contain the resultant "dtb" formed by applying
the "dtbo" overlay on the base "dtb", rather than the "dtbo" itself.
Hence, change "k3-j7200-evm-pcie1-ep.dtbo" to "k3-j7200-evm-pcie1-ep.dtb"
in the list of "dtbs".
Fixes: f43ec89bbc ("arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly
connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1
and SPI3 are independently pinned out. By default, the field
SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct
connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model
this functionality as a "reg-mux" device and based on the idle-state
property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3.
The register field description has been referred from J7200 TRM [1]
(Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions).
[1] https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add the "bootph-all" property to the "usb0" device-tree node. This is
required for the USB0 instance of USB to be functional at all stages
of USB DFU boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241220054550.153360-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The GIC Redistributor control range is mapped twice. Remove the extra
entry from the reg range.
Fixes: 5fc6b1b626 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-2-758b4d5b4a0a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The GIC Redistributor control register range is mapped twice. Remove
the extra entry from the reg range.
Fixes: f1d17330a5 ("arm64: dts: ti: Introduce base support for AM62x SoC")
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-1-758b4d5b4a0a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox
and memory carveouts used by these remote cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203174114.94751-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are
incomplete and may not be functional unless they are extended with a
chosen interrupt and connection to a remote processor.
Disable the Mailbox nodes in the dtsi files and only enable the ones
that are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203174114.94751-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This node is already defined in the included k3-am62x-sk-common.dtsi.
Remove this redefinition.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203164031.20211-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable support for mcu_i2c0 and add pinmux required to bring out the
mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Signed-off-by: Shreyash Sinha <s-sinha@ti.com>
Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com>
Link: https://lore.kernel.org/r/20241105091224.23453-1-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Ethernet boot requires CPSW node to be present starting from R5 SPL stage.
Add bootph-all property in CPSW MAC's eFuse node cpsw_mac_syscon to enable
this node during SPL stage along with later boot stages so that CPSW port
will get static MAC address.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20241114165331.1279065-1-c-vankar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Remove "ti,(rx|tx)-fifo-depth" properties which are both unused in the
kernel and undocumented. Most likely they are leftovers from downstream.
There are similar properties, but DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
represents the default value so adding them is not necessary.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241115193359.3618020-1-robh@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>
ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG
nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at
250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at
333MHz.
ICSSG_CORE clock will help get the most out of ICSSG as more cycles are
needed to fully support all ICSSG features.
This commit also changes assigned-clock-parents of coreclk-mux to
ICSSG_CORE clock from ICSSG_ICLK.
Performance update in dual mac mode
With ICSSG_CORE Clk @ 333MHz
Tx throughput - 934 Mbps
Rx throughput - 914 Mbps,
With ICSSG_ICLK clk @ 250MHz,
Tx throughput - 920 Mbps
Rx throughput - 706 Mbps
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241113110955.3876045-3-danishanwar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL and
therefore not configured.
This is necessary if the MCU domain is to program the TPS6594 MCU ESM
state machine, which is required to wire up the watchdog in a manner
that will reset the board.
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-2-102ddaa1bdc6@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>
In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL and
therefore not configured.
This is necessary if the MCU domain is to program the TPS6594 MCU ESM
state machine, which is required to wire up the watchdog in a manner
that will reset the board.
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-1-102ddaa1bdc6@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>
After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB devices. This requires that
the pin corresponding to the Type-A connector remains pulled up even after
the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup /
pulldown selection for the USB1_DRVVBUS pin and set its Deep Sleep state to
PULL_UP.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205120134.754664-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The behavior of pins in deep sleep mode can be configured by programming
the corresponding bits in the respective Pad Configuration register. Add
macros to support this.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205120134.754664-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add the missing vcc-supply property to the EEPROM node which resolves
the following warning:
at24 1-0051: supply vcc not found, using dummy regulator
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241101131427.3815341-4-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
Specify the regulator for the EEPROM supply voltage and associate it
with the EEPROM device. This resolves the following warning:
at24 0-0050: supply vcc not found, using dummy regulator
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241101131427.3815341-3-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
Specify I/0 voltage & core supply regulators used by the SII902x
HDMI bridge and make them known to the bridge.
This resolves the following warning:
sii902x 1-0039: supply iovcc not found, using dummy regulator
sii902x 1-0039: supply cvcc12 not found, using dummy regulator
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241101131427.3815341-2-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
The phyBOARD-Lyra connects only 16 pins to the SII902x HDMI bridge's RGB
input. The default 24-bit setting causes incorrect color output. Update
to 16-bit to match the hardware configuration.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241101131427.3815341-1-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
Add another entry in the wkup_conf for the syscon node, and then use
that for the syscon in opp-table.
Marking entire wkup_conf as "syscon", "simple-mfd" is wrong and needs to
be addressed similar to how other child-nodes in wkup_conf are implemented
in the same file.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241104063707.3604302-1-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP
table to enable this frequency
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-5-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Px can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
the OPP entries the SoC supports. A table of all these variants can be
found in its data sheet[0] for the AM62Px processor family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-4-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62Ax reference board is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table
to enable this OPP
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-3-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Ax can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
to only OPP entries the variant supports. A table of all these variants
can be found in it's data sheet[0] for the AM62Ax family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-2-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add Toradex Verdin Ivy carrier board support. One notable feature of Ivy
is the analog inputs. These inputs are multiplexed, allowing the same
input to measure either voltage or current. For current measurements,
a GPIO switch enables or disables the shunt resistor. This process is
automatically managed by the Linux kernel using the IIO and MUX
subsystems. Voltage measurement is always enabled, but the voltage
measured by the ADC is scaled by a cascade voltage divider. In the
device tree, the equivalent gain of the voltage divider is used, which
can be calculated as follows:
------------
+ |
.-.
R1=30K | |
| |
'-'
|-------------------
Analog Input (AIN) | |
.-. .-.
R2=10K | | R3=30K | |
| | | |
'-' '-'
| |
| |--------
| .-. +
| R4=10K | |
| | | ADC Input (Channels 0 and 1)
| '-'
- | | -
-----------| |--------
=== ===
GND GND
Vin = Analog Input (AIN)
Vout = ADC Input
Rth = Thevenin Equiv. Resistance
Vth = Thevenin Equiv. Voltage
RL = Load Resistor
R1 = 30K, R2 = 10K, R3 = 30K, R4 = 10K
RL = R4 = 10K
Rth = (R1 // R2) + R3 = 37500 Ohms
Vth = (Vin * R2) / (R1 + R2) = Vin/4;
Vout = (Vth * RL)/ (Rth + RL) = Vth/4.75 = Vin/19
Gain = Vout/Vin = 1/19
https://www.toradex.com/products/carrier-board/ivy-carrier-board
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20240924120044.130913-4-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add a label to ti-ads1015 node to make it easier to reference it
from other nodes.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20240924120044.130913-3-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Be default, R511 iand D19 are not populated on our phyBOARD-Electra.
This resistor and diode connect VCC_3V3_SW with VBAT and permanently
charge the RTC battery.
Enable trickle charge to charge the battery through the RTC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240911124251.702590-3-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240911124251.702590-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240911124251.702590-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The bus-width property was moved to k3-am64-main.dtsi.
See commit 0ae3113a46 ("arm64: dts: ti: k3-am6*: Fix bus-width property
in MMC nodes")
Signed-off-by: John Ma <jma@phytec.com>
Link: https://lore.kernel.org/r/20240926184918.3342719-2-jma@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The bus-width property was moved to k3-am64-main.dtsi.
See commit 0ae3113a46 ("arm64: dts: ti: k3-am6*: Fix bus-width property
in MMC nodes")
Signed-off-by: John Ma <jma@phytec.com>
Link: https://lore.kernel.org/r/20240926184918.3342719-1-jma@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add overlay to enable the PCIe0 instance of PCIe on AM642-EVM in
Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240930103413.3085689-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add overlay to enable the PCIE1 instance of PCIe on J7200-EVM in
Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241001093426.3401765-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The power switch used to power the SD card interface might have
more than 2ms turn-on time, increase the startup delay to 20ms to
prevent failures.
Fixes: 316b80246b ("arm64: dts: ti: add verdin am62")
Cc: stable@vger.kernel.org
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20241024130628.49650-1-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Fix Verdin AM62 on-SOM ADC compatible. Currently the hardware is not
correctly described in the DT, use the correct TI TLA2024 compatible that
matches what is assembled on the board.
The "ti,tla2024" compatible was introduced in Linux v5.19 and Verdin AM62
support was introduced in Linux v6.5.
The new DTB will not work on kernel older than v5.19, but this seems
unlikely to happen. U-Boot does not use the ADC node and a known Android 14
out-of-tree port uses a Linux Kernel 6.1.
With that said, despite this being a breaking change, it seems fair to
to not expect any regression because of it.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Link: https://lore.kernel.org/r/20241015113334.246110-1-jpaulo.silvagoncalves@gmail.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The clock IDs for multiple MCSPI instances across wakeup as
well as main domain in J7200 are incorrect when compared with
documentation [1]. This results in kernel crashes when the said
instances are enabled. Fix the clock ids to their appropriate
values.
[1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
Fixes: 8f6c475f4c ("arm64: dts: ti: k3-j7200: Add MCSPI nodes")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Link: https://lore.kernel.org/r/20241023104532.3438851-2-a-dutta@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Commit 0d0a0b4413 ("arm64: dts: ti: k3-j7200: fix main pinmux
range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1
due to a non-addressable region, but incorrectly represented the
ranges. As a result, the memory map for the pinctrl is incorrect. Fix
this by introducing the correct ranges.
The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0
Registers).
Padconfig starting addresses and ranges:
- 0 to 66: 0x11c000, 0x10c
- 68: 0x11c110, 0x004
- 71 to 73: 0x11c11c, 0x00c
- 89 to 90: 0x11c164, 0x008
The datasheet [2] doesn't contain PADCONFIG63 (Table 6-106. Pin
Multiplexing), but the pin is necessary for enabling the MMC1 CLKLP
pad loopback and should be included in the pinmux register map.
Due to the change in pinmux node addresses, change the pinmux node for
the USB0_DRVVBUS pin to main_pmx2. The offset has not changed since the
new main_pmx2 node has the same base address and range as the original
main_pmx1 node. All other pinmuxing done within J7200 dts or dtso files
only uses main_pmx0 which has not changed.
[1] https://www.ti.com/lit/pdf/spruiu1
[2] https://www.ti.com/lit/gpn/dra821u
Fixes: 0d0a0b4413 ("arm64: dts: ti: k3-j7200: fix main pinmux range")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20240926102533.398139-1-a-limaye@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, hbmc for enabling various bootmodes.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-12-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc1, usb0, usb1, ospi0 for enabling various bootmodes.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-11-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-10-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc1, ospi0 for enabling various bootmodes.
- eeprom for board detection
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-9-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes.
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-8-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adding bootph properties on leaf nodes imply that they are applicable to
the parent nodes as well. Bootloaders can derive the parent nodes when
bootph is available in the leaf nodes.
Remove the bootph-* properties from parent nodes as they are redundant.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-7-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- hbmc_mux for enabling Hyperflash support
- ESM nodes for enabling ESM support.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-6-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- hbmc_mux for enabling Hyperflash support
- ESM nodes for enabling ESM support.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-5-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-4-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The following nodes are being used in the bootloaders. Adds bootph-*
properties to the leaf nodes to enable bootloaders to utilise them.
Following adds bootph-* to
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-3-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adding bootph properties on leaf nodes imply that they are applicable to
the parent nodes as well. Bootloaders can derive the parent nodes when
bootph is available in the leaf nodes.
Remove the bootph-* properties from parent nodes as they are redundant.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-2-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ti,pa-stats phandles to k3-am64x-evm.dts. This is a phandle to
PA_STATS syscon regmap and will be used to dump IET related statistics
for ICSSG Driver
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-5-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add pa-stats nodes to k3-am64-main.dtsi for all ICSSG instances.
This is needed to dump IET related statistics for ICSSG Driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-4-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ti,pa-stats phandles to AM65x device trees. This is a phandle to
PA_STATS syscon regmap and will be used to dump IET related statistics
for ICSSG Driver
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://lore.kernel.org/r/20241014074527.1121613-3-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add pa-stats nodes to k3-am65-main.dtsi for all ICSSG instances.
This is needed to dump IET related statistics for ICSSG Driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-2-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update the RGMII delay to 2.5ns to improve performance. We use an
additional mapper board for the am62a7 phyBOARD Lyra which makes this
delay necessary.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241004221049.1155022-1-nmorrisson@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Drop the McASP AFIFOs for better audio latency. This adds back a
change that was lost while refactoring the device tree.
Fixes: 554dd562a5 ("arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Drop McASP AFIFOs")
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241002224754.2917895-1-nmorrisson@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
There are 3 instances of eQEP on AM64x. Only EQEP0 signals
can be routed to the user expansion so enable only EQEP0
in k3-am642-sk.dts.
Signed-off-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20240924220700.886313-6-jm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-6-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed.
Disable by default as this node is not complete until mailbox data
is provided in the board level DT.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed.
Disable by default as this node is not complete until mailbox data
is provided in the board level DT.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
We now configure the a53_opp_table to include a 1.4 GHz node and set our
VDD_CORE to 0.85v in the k3-am62-phycore-som.dtsi. This change is to
match our PMIC which is now set to output 0.85v by default.
This reverts commit 7a5775a3da.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Link: https://lore.kernel.org/r/20241001071916.1362213-3-ggiordano@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The am625 is capable of running at 1.4 GHz when VDD_CORE is increased
from 0.75V to 0.85V. Here we add a 1.4 GHz node to the a53_opp_table and
increase the VDD_CORE voltage accordingly.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241001071916.1362213-2-ggiordano@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This device is a subset of J784S4 and shares the same memory map and
thus the nodes are being reused from J784S4 to avoid duplication.
Here are some of the salient features of the J742S2 automotive grade
application processor:
The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.
Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch
( Refer Table 2-1 for Device comparison with J7AHP )
Link: https://www.ti.com/lit/pdf/spruje3 (TRM)
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-4-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Refactor J784s4-evm to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-2-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Refactor J784s4 SoC files to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-1-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Here is the "big" set of char/misc and other driver subsystem changes
for 6.12-rc1. Sorry for the delay, conference travel for the past two
weeks has this and my other pull requests showing up real late
in the cycle.
Lots of changes in here, primarily dominated by the usual IIO driver
updates and additions, but there are also small driver subsystem updates
all over the place. Included in here are:
- lots and lots of new IIO drivers and updates to existing ones
- interconnect subsystem updates and new drivers
- nvmem subsystem updates and new drivers
- mhi driver updates
- power supply subsystem updates
- kobj_type const work for many different small subsystems
- comedi driver fix
- coresight subsystem and driver updates
- fpga subsystem improvements
- slimbus fixups
- binder new feature addition for "frozen" notifications
- lots and lots of other small driver updates and cleanups
All of these have been in linux-next for a long time with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc driver updates from Greg KH:
"Here is the "big" set of char/misc and other driver subsystem changes
for 6.12-rc1.
Lots of changes in here, primarily dominated by the usual IIO driver
updates and additions, but there are also small driver subsystem
updates all over the place. Included in here are:
- lots and lots of new IIO drivers and updates to existing ones
- interconnect subsystem updates and new drivers
- nvmem subsystem updates and new drivers
- mhi driver updates
- power supply subsystem updates
- kobj_type const work for many different small subsystems
- comedi driver fix
- coresight subsystem and driver updates
- fpga subsystem improvements
- slimbus fixups
- binder new feature addition for "frozen" notifications
- lots and lots of other small driver updates and cleanups
All of these have been in linux-next for a long time with no reported
problems"
* tag 'char-misc-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (354 commits)
greybus: gb-beagleplay: Add firmware upload API
arm64: dts: ti: k3-am625-beagleplay: Add bootloader-backdoor-gpios to cc1352p7
dt-bindings: net: ti,cc1352p7: Add bootloader-backdoor-gpios
MAINTAINERS: Update path for U-Boot environment variables YAML
nvmem: layouts: add U-Boot env layout
comedi: ni_routing: tools: Check when the file could not be opened
ocxl: Remove the unused declarations in headr file
hpet: Fix the wrong format specifier
uio: Constify struct kobj_type
cxl: Constify struct kobj_type
binder: modify the comment for binder_proc_unlock
iio: adc: axp20x_adc: add support for AXP717 ADC
dt-bindings: iio: adc: Add AXP717 compatible
iio: adc: axp20x_adc: Add adc_en1 and adc_en2 to axp_data
w1: ds2482: Drop explicit initialization of struct i2c_device_id::driver_data to 0
tools: iio: rm .*.cmd when make clean
iio: adc: standardize on formatting for id match tables
iio: proximity: aw96103: Add support for aw96103/aw96105 proximity sensor
bus: mhi: host: pci_generic: Enable EDL trigger for Foxconn modems
bus: mhi: host: pci_generic: Update EDL firmware path for Foxconn modems
...
Add bootloader-backdoor-gpios which is required for enabling bootloader
backdoor for flashing firmware to cc1352p7.
Also fix the incorrect reset-gpio.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20240903-beagleplay_fw_upgrade-v4-2-526fc62204a7@beagleboard.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The K3 J722S-EVM platform is based on the J722S SoC which has one
single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN
voltage domain, and two C71x DSP subsystems in MAIN voltage domain.
The Inter-Processor communication between the A53 cores and these R5F
and DSP remote cores is achieved through shared memory and Mailboxes.
Thus, add the memory carveouts and enable the mailbox clusters required
for communication.
Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage
domain use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash during booting of remotecores. Usage is
described as below:
+===================+=============+
| Remoteproc Node | Timer Node |
+===================+=============+
| main_r5fss0_core0 | main_timer0 |
+-------------------+-------------+
| c7x_0 | main_timer1 |
+-------------------+-------------+
| c7x_1 | main_timer2 |
+-------------------+-------------+
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20240830161742.925145-3-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each
of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems
in MAIN voltage domain. Add the DT nodes to support Inter-Processor
Communication.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
[ refactoring changes to k3-j722s-main.dtsi ]
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240830161742.925145-2-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit 73f1f26e2e ("arm64: dts: ti: k3-am68-sk-som: Add support
for OSPI flash") introduced the flash node with discontinuous
partitions. Updating the partition offset to be continuous from
the previous partition to maintain linearity.
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Link: https://lore.kernel.org/r/20240828060830.555733-1-p-mantena@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
BeagleBoard.org BeagleY-AI is an easy to use, affordable open source
hardware single board computer based on the Texas Instruments AM67A,
which features a quad-core 64-bit Arm CPU subsystem, 2 general-purpose
digital-signal-processors (DSP) and matrix-multiply-accelerators (MMA),
GPU, vision and deep learning accelerators, and multiple Arm Cortex-R5
cores for low-power, low-latency GPIO control.
https://beagley-ai.org/https://openbeagle.org/beagley-ai/beagley-ai
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://lore.kernel.org/r/20240829213929.48540-2-robertcnelson@gmail.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Each Ethernet PHY on IOT2050 platforms drives 3 LEDs whose triggers
can be configured to signal link properties such as connection status
or speed.
Declare the LEDs, exposing their trigger controls to userspace.
Signed-off-by: Diogo Ivo <diogo.ivo@siemens.com>
Link: https://lore.kernel.org/r/20240829-ivo-iot2050_leds-v1-1-792a512b2178@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Error Signaling Module (ESM) instances in MCU and MAIN domains,
set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt
Sources.
There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not
possible to reset the CPU using watchdog and ESM0 configuration.
However add ESM instances for device completion.
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] http://www.ti.com/lit/pdf/spruid7
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-7-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Error Signaling Module (ESM) instances in MCU and MAIN domains,
set ESM interrupt sources for rti as per TRM [0] 10.4 Interrupt
Sources.
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] https://www.ti.com/lit/pdf/spruj16
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-2-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add comments to describe what interrupt sources are routed to ESM
modules.
There is no functional change.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-5-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Fix interrupt sources for rti routed to the ESM0 as per [0], in 10.4
Interrupt Sources
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] https://www.ti.com/lit/pdf/spruj83
Fixes: b5080c7c1f ("arm64: dts: ti: k3-am62p: Add nodes for more IPs")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-3-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Remove 'reserved' status for MCU ESM node. Watchdog reset is
propagated through ESM0 to MCU ESM to reset the CPU, so enable MCU ESM
to reset the CPU with watchdog timeout.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-4-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Fix the gpio hog node name to p15-hog to match up with gpio-hog
convention. This fixes dtbs_check warning:
p15: $nodename:0: 'p15' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'
Acked-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240830102822.3970269-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Rename the pin mux and gpio-hog node names to match up with binding
rules. This fixes dtbs_check warnings:
'gpmc0-pins-default' does not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+'
'gpio0-36' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'
While at it, change the phandle name to be consistent with the pinctrl
naming.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20240830113137.3986091-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although
not used currently by the Linux FSS driver, these regions belong to
the FSS and should be included in the ranges mapping.
While here, a couple of these numbers had missing zeros which was
hidden by odd alignments, fix both these issues.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://lore.kernel.org/r/20240828172956.26630-5-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
