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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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arm64: dts: ti: Refactor J784s4 SoC files to a common file
Refactor J784s4 SoC files to a common file which uses the superset device to allow reuse in j742s2-evm which uses the subset part. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-1-6a7aa2736797@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Manorit Chawdhry
Vignesh Raghavendra
parent
9852d85ec9
commit
9cc161a450
148
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
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148
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
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@ -0,0 +1,148 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for J784S4 and J742S2 SoC Family
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*
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* TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
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* TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
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*
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* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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L2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a72_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a72-pmu";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@100000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
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<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
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<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
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<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
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<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
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<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
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<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
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<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
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<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
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<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
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<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
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<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
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<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
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<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
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<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
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<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
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<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
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<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
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<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
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<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
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/* MCUSS_WKUP Range */
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
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cbass_mcu_wakeup: bus@28380000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
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};
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};
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thermal_zones: thermal-zones {
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#include "k3-j784s4-j742s2-thermal-common.dtsi"
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};
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};
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/* Now include peripherals from each bus segment */
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#include "k3-j784s4-j742s2-main-common.dtsi"
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#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi"
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2671
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
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2671
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
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* Device Tree Source for J784S4 and J742S2 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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File diff suppressed because it is too large
Load Diff
@ -8,18 +8,11 @@
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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#include "k3-j784s4-j742s2-common.dtsi"
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/ {
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model = "Texas Instruments K3 J784S4 SoC";
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compatible = "ti,j784s4";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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@ -174,130 +167,6 @@ cpu7: cpu@103 {
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next-level-cache = <&L2_1>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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L2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a72_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a72-pmu";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@100000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
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<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
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<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
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<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
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<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
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<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
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<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
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<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
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<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
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<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
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<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
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<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
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<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
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<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
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<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
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<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
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<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
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<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
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<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
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<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
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/* MCUSS_WKUP Range */
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
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cbass_mcu_wakeup: bus@28380000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
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};
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};
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thermal_zones: thermal-zones {
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#include "k3-j784s4-thermal.dtsi"
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};
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};
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/* Now include peripherals from each bus segment */
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#include "k3-j784s4-main.dtsi"
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#include "k3-j784s4-mcu-wakeup.dtsi"
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