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arm64: dts: ti: k3-am62p: Add gpio-ranges properties

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On the AM62P platform we have no single 1:1 relation regarding index
of GPIO and pin controller. The GPIOs and pin controller registers
have mapping and holes in the map. These have been extracted from the
AM62P data sheet.

MCU pinctrl definition is shared as it is common between AM62P and
J722S, but that is not the case for main domain.

Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20240627162539.691223-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Nishanth Menon 2024-06-27 11:25:38 -05:00 committed by Vignesh Raghavendra
parent 50d9981fa1
commit d72d73a44c
2 changed files with 25 additions and 0 deletions
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8
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
View File

@ -12,7 +12,15 @@ mcu_pmx0: pinctrl@4084000 {
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
pinctrl-single,gpio-range =
<&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
<&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
<&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
bootph-all;
mcu_pmx_range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
mcu_esm: esm@4100000 {

17
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
View File

@ -42,10 +42,27 @@ &inta_main_dmss {
ti,interrupt-ranges = <5 69 35>;
};
&main_pmx0 {
pinctrl-single,gpio-range =
<&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
<&main_pmx0_range 33 92 PIN_GPIO_RANGE_IOPAD>,
<&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
<&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
<&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
main_pmx0_range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
&main_gpio0 {
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
<&main_pmx0 70 72 22>;
ti,ngpio = <92>;
};
&main_gpio1 {
gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
ti,ngpio = <52>;
};