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From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/** @file
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Internal function to get spin lock alignment.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "BaseSynchronizationLibInternals.h"
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/**
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Internal function to retrieve the architecture specific spin lock alignment
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requirements for optimal spin lock performance.
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@return The architecture specific spin lock alignment.
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**/
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UINTN
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InternalGetSpinLockProperties (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEbx;
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UINTN FamilyId;
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UINTN ModelId;
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UINTN CacheLineSize;
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//
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// Retrieve CPUID Version Information
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//
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AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);
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//
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// EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size)
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//
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CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;
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//
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// Retrieve CPU Family and Model
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//
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if (FamilyId == 0x0f) {
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//
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// In processors based on Intel NetBurst microarchitecture, use two cache lines
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//
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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if (ModelId <= 0x04 || ModelId == 0x06) {
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CacheLineSize *= 2;
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}
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}
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return CacheLineSize;
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}
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