mirror of
https://git.proxmox.com/git/mirror_edk2
synced 2025-10-28 16:10:44 +00:00
From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> |
||
|---|---|---|
| .. | ||
| GccInline.c | ||
| InterlockedCompareExchange16.asm | ||
| InterlockedCompareExchange16.c | ||
| InterlockedCompareExchange32.asm | ||
| InterlockedCompareExchange32.c | ||
| InterlockedCompareExchange64.asm | ||
| InterlockedCompareExchange64.c | ||
| InterlockedDecrement.asm | ||
| InterlockedDecrement.c | ||
| InterlockedIncrement.asm | ||
| InterlockedIncrement.c | ||
| InternalGetSpinLockProperties.c | ||