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From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> |
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| .. | ||
| AArch64 | ||
| Arm | ||
| Ebc | ||
| Ia32 | ||
| Ipf | ||
| X64 | ||
| BaseSynchronizationLib.inf | ||
| BaseSynchronizationLib.uni | ||
| BaseSynchronizationLibInternals.h | ||
| Synchronization.c | ||
| SynchronizationGcc.c | ||
| SynchronizationMsc.c | ||