mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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6dad43bb11
The SiFive Performance P650 core (including the vector-enabled P670 and area-optimized P450/P470 variants) updates the P550 microarchitecture. It brings in the debug, trace, and counter events from newer Bullet cores, and adds new events for iTLB and dTLB multi-hits. All other PMU events are unchanged from the P550 core. Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Ian Rogers <irogers@google.com> Tested-by: Ian Rogers <irogers@google.com> Tested-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250213220341.3215660-8-samuel.holland@sifive.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
1022 B
1022 B
| 1 | # Format: |
|---|---|
| 2 | # MVENDORID-MARCHID-MIMPID,Version,JSON/file/pathname,Type |
| 3 | # |
| 4 | # where |
| 5 | # MVENDORID JEDEC code of the core provider |
| 6 | # MARCHID base microarchitecture of the hart |
| 7 | # MIMPID unique encoding of the version |
| 8 | # of the processor implementation |
| 9 | # Version could be used to track version of JSON file |
| 10 | # but currently unused. |
| 11 | # JSON/file/pathname is the path to JSON file, relative |
| 12 | # to tools/perf/pmu-events/arch/riscv/. |
| 13 | # Type is core, uncore etc |
| 14 | # |
| 15 | # |
| 16 | #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType |
| 17 | 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core |
| 18 | 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core |
| 19 | 0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core |
| 20 | 0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core |
| 21 | 0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core |
| 22 | 0x5b7-0x0-0x0,v1,thead/c900-legacy,core |
| 23 | 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core |
| 24 | 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core |