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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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26bc201954
AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie0_ep" device tree node. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250610054920.2395509-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
53 lines
1.3 KiB
Plaintext
53 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
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* AM642 EVM.
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*
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* AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/*
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* Since Root Complex and Endpoint modes are mutually exclusive
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* disable Root Complex mode.
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*/
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&pcie0_rc {
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status = "disabled";
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};
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&cbass_main {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic500>;
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pcie0_ep: pcie-ep@f102000 {
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compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
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reg = <0x00 0x0f102000 0x00 0x1000>,
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<0x00 0x0f100000 0x00 0x400>,
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<0x00 0x0d000000 0x00 0x00800000>,
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<0x00 0x68000000 0x00 0x08000000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "mem";
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
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max-link-speed = <2>;
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num-lanes = <1>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "fck";
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max-functions = /bits/ 8 <1>;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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bootph-all;
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ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
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};
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};
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