3 Commits

Author	SHA1	Message	Date
Hrushikesh Salunke	26bc201954	arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep" ... AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie0_ep" device tree node. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250610054920.2395509-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>	2025-06-21 22:17:48 +05:30
Andrew Davis	4e7ad3b446	arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region ... This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis <afd@ti.com> [j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250402113201.151195-6-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>	2025-04-18 13:28:12 -05:00
Siddharth Vadapalli	34d7b84193	arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP mode ... Add overlay to enable the PCIe0 instance of PCIe on AM642-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20240930103413.3085689-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>	2024-10-28 22:21:48 +05:30