These were initially added because some software was checking for their
presence. However, the device is not NUMA, so adding these is wrong and
hence they should be removed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Two cleanups which were missed on mailing lists - align GPIO node names
with DT bindings for Mediatek mt7622 and Nvidia Tegra210-p2894.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmgjIRIQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD132YD/95kvOhmdQmd1qvc+bVSgLThHr2FCvX0VT7
B8Yk8XRalngADyG4Qda0m4XA9lZQ1jiG2i0fWBb2aEXqMDgve4jvq1J9BoNxIloY
eR+ATlRnmIDBiAvGozvPhp/WIPCm17RDscCl8XvJCiEXrRfKUQuVljtj/aOLbeWZ
NKjRPPdXQlKjaBUSUv3geW2z68uPRKEXsrKf5/v8jGAFUoWF7y7eascGuUz/ZQZr
hB11emIOteQ824vsE0rkE5V4a2Szaro50+xryvGw9Ja0YaoXwyog+wEiRgvySYnc
YyTfKjccUYgyIdTjBnIECiTEwlBiy6InPzBfVNx8ezlVFiuPTzt7Yv0v/acKx/D7
OXAs1yEEWYSu5NoHbhHxdGaHbtVScbHwPdS1PV7WPpBD0IBdCorSJKzKF+hNHdjz
Javm/bD5B8ichKJKpPPOWmPiY/8h7TQFUsuzd+zDY4CZQEnHEdNCeC//RZ/AOdIm
KYrcD0JL/NliaDh2i3wDs1AN6rV45Uhv6mBwjFSJfZBhXPqB8ns7wD08PIeyuNoq
Pv6NllWrNoHKlyz+pXYgDIzM7a6iDfCAjydO6gkS8EgE/tYKTaJKDyfvs7NPM5MU
VONtP8DZoGfm7u45JrHMLwvsR4HRaz2IjouAA2C/k6z4SXsICWAODXWjjXX0fPtv
NYg3gFLLKw==
=vSix
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguCdcACgkQmmx57+YA
GNkaHBAAtJ24IruvIM7TLO1z7yHnWvaGeCzks1AR8yP3Hhl8HppwsQ9UKI0GOiki
iIiYlc4RNJCg79HjA9375UenmzHyC62dcD7fCHZxfWKoNQm/+KTA8WbH2iELZm6A
cBYr+G+AqMHKrNC/JFlVtxULy1HQY+/8ktKbg1YG8vpnBiGTAmZuDk5lgjwB/5qI
0Y8GK/3mUY5AWs7oXgPcBJmkD8mn9f/iYH8YhDfrBLMY6hGelEBFdezvoyBQhE1o
C+hZ06A9adS+GUlOHNRh83F3FbaRqmKDixxn7WGaXOxq5/e8OPc50zEdZPvNtZPY
DhGGiPMexG8+qVCJC+rSsmZedhHHwEjWQlTj3WxJ4RgbhfjhZRHbaMXcD83S6uVG
YF9Og1PiL9T9irw1yLZYNFZTSILr4a7I5oXOS/mlgufU37sW6RZDq1XHZLGEB435
MU2ubBC8oZcswwKMBfekk5+Ah7cGlW/DZrZnj5FqYuMFQWaAgWc53t1YLE70cZtU
litnjKeol9uSKUc2QgISth8MXSrSll+YqAv5A/YdRjcF6uLDWZPJ/Bo9tsgXtSj+
uikuW/0IBLztu3NMe1OaYI9mgMISRH4bn6ClgTfevm1IVIkFZ6hVWCkF9Mi9DyOl
rP4jg9KvwQ3S2HXtSI9QJjKLwc6Gt5CsGq5FMT94PaByjovqH3s=
=QSN1
-----END PGP SIGNATURE-----
Merge tag 'dt64-cleanup-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM64 DTS for v6.16
Two cleanups which were missed on mailing lists - align GPIO node names
with DT bindings for Mediatek mt7622 and Nvidia Tegra210-p2894.
* tag 'dt64-cleanup-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred style
arm64: dts: mediatek: mt7622: Align GPIO hog name with bindings
Link: https://lore.kernel.org/r/20250513104216.25803-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This enables HDMI CEC and routes it to the HDMI port on all supported
Tegra210, Tegra186, and Tegra194 devkits.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-4-b6337b66ccad@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
The tegra_cec driver only declares support up to Tegra210 and will not
declare support for Tegra186 or Tegra194. Thus list a fallback
compatible for these chips to tegra210-cec as they work as-is with the
existing driver.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-2-b6337b66ccad@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
If a serial-tegra interface does not have an alias, the driver fails to
probe with an error:
serial-tegra 70006300.serial: failed to get alias id, errno -19
This prevents the bluetooth device from being accessible.
Fixes: 6eba6471bb ("arm64: tegra: Wire up Bluetooth on Jetson TX1 module")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Link: https://lore.kernel.org/r/20250420-tx1-bt-v1-1-153cba105a4e@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
This was done for Tegra194 and Tegra234 in 2838cfd, but Tegra186 was not
part of that change. The same reasoning for that commit also applies to
Tegra186, plus keeping the archs as close to each other as possible makes
it easier to compare between them and support features concurrently.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250419-tegra186-host1x-addr-size-v1-1-a7493882248d@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
The gpu node originally was explicitly left disabled as it was expected
for the bootloader to enable it. However, this is only done in u-boot.
If u-boot is not in the boot chain, this will never be enabled. Other
Tegra210 devices already explicitly enable the gpu, so make p2180 match.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250420-tx1-gpu-v1-1-d500de18e43e@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
The gpu node originally was explicitly left disabled as it was expected
for the bootloader to enable it. However, this is only done in U-Boot.
If U-Boot is not in the boot chain, this will never be enabled. Other
Tegra186 devices already explicitly enable the GPU, so make p3310 match.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250426-tx2-gpu-v1-1-fa1c78dcdbdc@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
The referenced commit only removed some of the names, missing all that
weren't in use at the time. The commit removes the rest.
Fixes: 71de0a054d ("arm64: tegra: Drop serial clock-names and reset-names")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250428-tegra-serial-fixes-v1-1-4f47c5d85bf6@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
This is based on the existing configuration of the Jetson TX2 NX devkit.
The fan and thermal characteristics of the two devkits are similar, so
using the same configuration.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250427-tx2-therm-v1-1-65ddb4314723@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devkits are similar, so using the same configuration.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250501-tx1-therm-v2-1-abdb1922c001@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to
99.99 MHz using PLLC as the parent clock. These frequencies enable
Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL
and clock divider limitations. Introduce IOMMU property which is
needed for internal DMA transfers.
Signed-off-by: Vishwaroop A <va@nvidia.com>
Link: https://lore.kernel.org/r/20250506152350.3370291-2-va@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
This contains a patch to remove an unusable key that was erroneously
exposed as well as a fix to support GPUs with a large amount of video
memory on IGX Orin.
Finally, some additional devices, such as a temperature sensor, are
enabled on Jetson TX1, the output voltage of some pins is adjusted and
the VDD_LCD_1V8_DIS power supply now uses the correct enable GPIO.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmfLL9MACgkQ3SOs138+
s6Eoeg/+IEbLEwrIe1YugGzBF99Bhyaffvbh8GM/tp/EUyyrwOvzN1ROk7EFbtSY
WyHWPoajqyUvCccHG+ZaB/tLIVjgHZH3SZ2WZuoI7q0mc1n8yBkw3qdw/WcVh9ud
LeTaFR6059TE3cVZBDeO5AUsamo7EZLoypLY6WKZe/4VEC2SCcs3ouF1j6AazONa
yTFmALoj1s4Aerr2kJfn5HMOYh1aEfmMqm3g+RnXcp/WRGnkoh1L0St+9n30krC/
rZfWPM8o06jTu+SJmYJOWcXaHFs5rroV4MWZg0joez1tMZY3pHTBrJSZO1z+hizK
8p7FtNbUILcVo9PXFZ5lOfm0l08mQ5Xl2YkWoSsXbxbc42UAALlhfN5fmbJ1v2sv
iRxuaXoNlFoVrvEagGY4r0J/pPLU0OuAGIemob/oY42+eRVIUbixZ9naBlB8yMqh
SaQ9ciTwdqq+EYvjgj/6HKC9cGr8MMtZEfkN3oLCD0gqt6Lzq9OH5f1x6/0YI3JX
7B72rfwukT3o0mRcJIUz3D/2W9FHQXZydoExeRIGm8o0bDFzFRi/gf4zgW1LI64/
DdgnUK7I6R7fgcJRwgPTe1OmhyCbP865KhgDGuPR8DvctAiGeK0PdAwXYIbDi0OP
8yHsUHVzEh7tPMhu9dQR/oL0OwL7ngVYWSjZ0NRbaDw8eaD0Nks=
=f5mG
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUaooACgkQYKtH/8kJ
UifbuRAAuv5D14B2Aqnx24EDIPX4ztabKekBINWC1bMcMqqMOTgiWqsxRg07qT8J
eKV1MMAquk889MqsrKhr48EKX4QznboFkZwI4UrLd+kzM02puZOQtkrRkTKL02Q4
p9zAScx6MIhQseuY10+GfYC6d1y+F89qzrSoDKvD4kMEblNOqT/54iZwPtDiYZi5
04+Ou0/96ikV89M6p6MRcl6R3QanA85rJwHiS+3DW+JFz0VGQ39Dmi3N9ubT5Psp
prjodBjtfgzKvuArjVa2RiRe6jwPFtQiOiUEr60mjUJCxOZrkgWTzK6PCyGpiBd9
9TUkSMss7lB2d4AXVOgQtMxo5yyGD2L6X+2FPWTQstvo5Je/iDhVPkPQUTAWwZB4
WLVzhLXLE5jd/zto80Q5icKVIllGRsJeW/pythIDr9YkpB6Zo/lq8MH/ycJtP1R2
ku1quhJYJ8gp1GE6iwYB3JgCD7gluvDZ/kkVMfZH3vOcUSp4PZ1OMSLhg+a/sUYZ
Pv9l2GlUQ5C6H6yf/F8VQKLT5xZCo/iQw6AdJlPCv0r+hNxgDjvhcURO7V1zxRbt
Y6DwChii2SXJyYu/Cvd4KW6Kn3603OxzcJEcb+/3tC9gzdBVGtU1LOnvyic7rmZm
9iqIht8NtHreshVt/VEriUFwbs/w3IcHZUZ6hZNduFF8ZvM9Mw8=
=0hwA
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.15-rc1
This contains a patch to remove an unusable key that was erroneously
exposed as well as a fix to support GPUs with a large amount of video
memory on IGX Orin.
Finally, some additional devices, such as a temperature sensor, are
enabled on Jetson TX1, the output voltage of some pins is adjusted and
the VDD_LCD_1V8_DIS power supply now uses the correct enable GPIO.
* tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: p2180: Add TMP451 temperature sensor node
arm64: tegra: p2597: Enable TCA9539 as IRQ controllers
arm64: tegra: Define pinmuxing for gpio pads on Tegra210
arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator
arm64: tegra: Resize aperture for the IGX PCIe C5 slot
arm64: tegra: Remove the Orin NX/Nano suspend key
Link: https://lore.kernel.org/r/20250307174938.3456275-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As the gpio pads are capable of operating at either 1.8V or 3.3V add
both options to the pinmuxing so that the appropriate level can be set
depending on the voltage of the regulator driving the pads.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-2-80fb84ac48c6@tecnico.ulisboa.pt
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the board schematics the enable pin of this regulator is
connected to gpio line #9 of the first instance of the TCA9539
GPIO expander, so adjust it.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-1-80fb84ac48c6@tecnico.ulisboa.pt
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some discrete graphics cards such as the NVIDIA RTX A6000 support
resizable BARs. When connecting an A6000 card to the NVIDIA IGX Orin
platform, resizing the BAR1 aperture to 8GB fails because the current
device-tree configuration for the PCIe C5 slot cannot support this.
Fix this by updating the device-tree 'reg' and 'ranges' properties for
the PCIe C5 slot to support this.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20250116151903.476047-1-jonathanh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
As per the Orin Nano Dev Kit schematic, GPIO_G.02 is not available
on this device family. It should not be used at all on Orin NX/Nano.
Having this unused pin mapped as the suspend key can lead to
unpredictable behavior for low power modes.
Orin NX/Nano uses GPIO_EE.04 as both a "power" button and a "suspend"
button. However, we cannot have two gpio-keys mapped to the same
GPIO. Therefore remove the "suspend" key.
Cc: stable@vger.kernel.org
Fixes: e63472eda5 ("arm64: tegra: Support Jetson Orin NX reference platform")
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
Signed-off-by: Ivy Huang <yijuh@nvidia.com>
Link: https://lore.kernel.org/r/20250206224034.3691397-1-yijuh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove "regulator-ramp-delay-scale" property which is both unused in the
kernel and undocumented. Most likely they are leftovers from downstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250305224952.2995841-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
For interrupt-map entries, the DTS specification requires
that #address-cells is defined for both the child node and the
interrupt parent. For the PCIe interrupt-map entries, the parent
node ("gic") has not specified #address-cells. The existing layout
of the PCIe interrupt-map entries indicates that it assumes
that #address-cells is zero for this node.
Explicitly set #address-cells to zero for "gic" so that it complies
with the device tree specification.
NVIDIA EDK2 works around this issue by assuming #address-cells
is zero in this scenario, but that workaround is being removed and so
this update is needed or else NVIDIA EDK2 cannot successfully parse the
device tree and the board cannot boot.
Fixes: ec142c44b0 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20241213235602.452303-1-bgriffis@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
Access to safety cluster engine (SCE) fabric registers was blocked
by firewall after the introduction of Functional Safety Island in
Tegra234. After that, any access by software to SCE registers is
correctly resulting in the internal bus error. However, when CPUs
try accessing the SCE-fabric registers to print error info,
another firewall error occurs as the fabric registers are also
firewall protected. This results in a second error to be printed.
Disable the SCE fabric node to avoid printing the misleading error.
The first error info will be printed by the interrupt from the
fabric causing the actual access.
Cc: stable@vger.kernel.org
Fixes: 302e154000 ("arm64: tegra: Add node for CBB 2.0 on Tegra234")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Ivy Huang <yijuh@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20241218000737.1789569-3-yijuh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
The compatible string for the Tegra DCE fabric is currently defined as
'nvidia,tegra234-sce-fabric' but this is incorrect because this is the
compatible string for SCE fabric. Update the compatible for the DCE
fabric to correct the compatible string.
This compatible needs to be correct in order for the interconnect
to catch things such as improper data accesses.
Cc: stable@vger.kernel.org
Fixes: 302e154000 ("arm64: tegra: Add node for CBB 2.0 on Tegra234")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Ivy Huang <yijuh@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20241218000737.1789569-2-yijuh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
Define the sdr104-specific offsets, preventing the driver from
defaulting to the 1.8V offsets, which cause the system to hang during
the SDR104 mode calibration.
The zeroing of these values was chosen since it restores functionality
and no better suggestions are provided by the Tegra X1 TRM.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The dtschema requires to specify common ancestor which all SDIO chips are
derived from, so add accordingly.
Fixes: a50d5dcd28 ("arm64: tegra: Wire up WiFi on Jetson TX1 module")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202409030438.8tumAnp1-lkp@intel.com
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The existing tegra234-p3737-0000+p3701-0000.dtb is compatible
with the following modules:
p3701-0000
p3701-0004
p3701-0005
Add support for p3701-0008. Move data that is common to all SKUs
to a new file called tegra234-p3737-0000+p3701.dtsi. Update Makefile.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
One of the key differences between p3701-0000 and p3701-0008 is the
temperature range. Add this info for p3701-0008.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
All SKUs of the p3701 module contain a temp sensor connected to the
BPMP I2C. Move the associated nodes from tegra234-p3701-0008.dtsi
to tegra234-p3701.dtsi. Add missing compatible.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some padctl supply nodes currently reside in board file, when they
should reside on module level. The nodes are part of module,
not board. Move these nodes to the correct AGX Orin
module file.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some of the nodes inside the AGX Orin module file are in the
wrong location. In particular, the SD card interface and
two of the PCIe regulators in the module file should instead
reside in the board file. These components are not part of the
module. They are part of the carrier board. Move these
nodes to the correct location.
Fixes: cd42b26a52 ("arm64: tegra: Add regulators required for PCIe")
Fixes: d71b893a11 ("arm64: tegra: Add Tegra234 SDMMC1 device tree node")
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Current IGX Orin structure has both a top-level module+board
file as well as a board file. Most of the data in the board-file
is closely related to the module itself. The benefit of this
extra file is outweighed by the additional complexity. Merge
the board file into the module+board file for simplicity.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current AGX Orin structure has both a top-level module+board
file as well as a board file. Most of the data in the board-file
is closely related to the module itself. The benefit of this
extra file is outweighed by the additional complexity. Merge
the board file into the module+board file for simplicity.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AGX Orin module boards contain common nodes that can
be moved to the included module dtsi. This eliminates
redundancy within the files and reduces lines of code.
Data from tegra234-p3701-0000 and tegra234-p3701-0008 that
is common is now in tegra234-p3701.dtsi.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
P2180 modules have WiFi in form of BCM4354 chip, and kernel driver
supports this one, so enable it for all users. The necessary calibration
file can be obtained from Jetson Linux Archive. nvram.txt file is
located in "Driver Package (BSP)" in
nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb
archive. The rest of necessary blobs can be obtained from official
Linux Firmware repository or (newer ones) from Infineon
ifx-linux-firmware repository (look in older releases).
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
P2180 modules have Bluetooth in form of BCM4354 chip, and kernel driver
supports this one, so enable it for all users. The necessary firmware
can be obtained from Jetson Linux Archive. bcm4354.hcd file is located
in "Driver Package (BSP)" in
nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb
archive.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
One INA3221 sensor is located on P2180 module and the other two are on
P2597 base board.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add implementation details for Orin NX/Nano PCIe EP on C4.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add PCIe C4 EP controller definition in device tree for Tegra234
devices.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the definition for the wp-gpio of the P2597's external card slot,
enabling this functionality.
Tested on a P2597 board.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
