mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-11-15 22:43:55 +00:00
2b55915d27
Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.
Fixes: bc47b2217f ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
160 lines
2.1 KiB
Plaintext
160 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/* Copyright (c) 2020-2021 Microchip Technology Inc */
|
|
|
|
/dts-v1/;
|
|
|
|
#include "mpfs.dtsi"
|
|
#include "mpfs-icicle-kit-fabric.dtsi"
|
|
|
|
/* Clock frequency (in Hz) of the rtcclk */
|
|
#define RTCCLK_FREQ 1000000
|
|
|
|
/ {
|
|
model = "Microchip PolarFire-SoC Icicle Kit";
|
|
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
|
|
|
|
aliases {
|
|
ethernet0 = &mac1;
|
|
serial0 = &mmuart0;
|
|
serial1 = &mmuart1;
|
|
serial2 = &mmuart2;
|
|
serial3 = &mmuart3;
|
|
serial4 = &mmuart4;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial1:115200n8";
|
|
};
|
|
|
|
cpus {
|
|
timebase-frequency = <RTCCLK_FREQ>;
|
|
};
|
|
|
|
ddrc_cache_lo: memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x80000000 0x0 0x2e000000>;
|
|
status = "okay";
|
|
};
|
|
|
|
ddrc_cache_hi: memory@1000000000 {
|
|
device_type = "memory";
|
|
reg = <0x10 0x0 0x0 0x40000000>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&core_pwm0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio2 {
|
|
interrupts = <53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>,
|
|
<53>, <53>, <53>, <53>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mac0 {
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&mac1 {
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy1>;
|
|
status = "okay";
|
|
|
|
phy1: ethernet-phy@9 {
|
|
reg = <9>;
|
|
};
|
|
|
|
phy0: ethernet-phy@8 {
|
|
reg = <8>;
|
|
};
|
|
};
|
|
|
|
&mbox {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmc {
|
|
bus-width = <4>;
|
|
disable-wp;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
status = "okay";
|
|
};
|
|
|
|
&mmuart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmuart2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmuart3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmuart4 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
};
|
|
|
|
&refclk {
|
|
clock-frequency = <125000000>;
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&syscontroller {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
};
|