Nicholas Kazlauskas 9cb2f2df66 drm/amd/display: Fix updating infoframe for DCN3.1 eDP ... [Why] We're only treating TMDS as a valid target for infoframe updates which results in PSR being unable to transition from state 4 to state 5. [How] Also allow infoframe updates for DCN3.1 - following how we handle this path for earlier ASIC as well. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-07-08 15:15:03 -04:00
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acp
amdgpu	drm/amdgpu: Return error if no RAS	2021-07-08 15:13:07 -04:00
amdkfd	drm/amdkfd: Maintain svm_bo reference in page->zone_device_data	2021-07-01 00:05:41 -04:00
display	drm/amd/display: Fix updating infoframe for DCN3.1 eDP	2021-07-08 15:15:03 -04:00
include	drm/amd/display: DMUB Outbound Interrupt Process-X86	2021-07-08 15:14:36 -04:00
pm	drm/amdgpu: The I2C IP doesn't support 0 writes/reads	2021-07-08 15:12:51 -04:00