Nicholas Kazlauskas 9cb2f2df66 drm/amd/display: Fix updating infoframe for DCN3.1 eDP ... [Why] We're only treating TMDS as a valid target for infoframe updates which results in PSR being unable to transition from state 4 to state 5. [How] Also allow infoframe updates for DCN3.1 - following how we handle this path for earlier ASIC as well. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-07-08 15:15:03 -04:00
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amdgpu_dm	drm/amd/display: Add Freesync HDMI support to DM with DMUB	2021-07-08 15:14:55 -04:00
dc	drm/amd/display: Fix updating infoframe for DCN3.1 eDP	2021-07-08 15:15:03 -04:00
dmub	drm/amd/display: DMUB Outbound Interrupt Process-X86	2021-07-08 15:14:36 -04:00
include	drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN	2021-06-22 16:51:45 -04:00
modules	drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN	2021-06-22 16:51:45 -04:00
Kconfig	drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN	2021-06-22 16:51:45 -04:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO