mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-11-24 20:17:16 +00:00
d46392bbf5
* Support for cbo.zero in userspace. * Support for CBOs on ACPI-based systems. * A handful of improvements for the T-Head cache flushing ops. * Support for software shadow call stacks. * Various cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVJAJoTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiWZrD/9ECV/0tuX5LbS56kA0ElkwiakyIVGu ZVuF26yGJ6w+XvwnHPhqKNVN0ReYR6s6CwH1WpHI5Du9QHZGQU3DKJ43dFMTP3Dn dQFli7QJ+tsNo1nre8NZWKj5Ac+Cu906F794qM0q0XrZmyb9DY3ojVYJAYy+dtoo /9gwbB7P0GLyDlURLn48oQyz36WQW3CkL5Jkfu+uYwnFe9DAFtfakIKq5mLlNuaH PgUk8pAVhSy2GdPOGFtnFFhdXMrTjpgxdo62ZIZC0lbsts26Dxp95oUygqMg51Iy ilaXkA2U1c1+gFQNpEove7BVZa5708Kaj6RLQ3/kAJblAzibszwQvIWlWOh7RVni 3GQAS7/0D0+0cjDwXdWaPIaFFzLfi3bDxRYkc7n59p6nOz+GrxnSNsRPQJGgYxeU oTtJfaqWKntm72iutiHmXgx/pvAxWOHpqDnSTlDdtjvgzXCplqBbxZFF/azj30o5 jplNW5YvdvD9fviYMAoGSOz03IwDeZF5rMlAhqu6vXlyD2//mID82yw/hBluIA3+ /hLo5QfTLiUGs9nnijxMcfoyusN6AXsJOxwYdAJCIuJOr78YUj0S974gd9KvJXma KedrwRVwW7KE7CwY1jhrWBsZEpzl8YrtpMDN47y4gRtDZN8XJMQ+lHqd+BHT/DUO TGUCYi5xvr6Vlw== =hKWl -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for cbo.zero in userspace - Support for CBOs on ACPI-based systems - A handful of improvements for the T-Head cache flushing ops - Support for software shadow call stacks - Various cleanups and fixes * tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (31 commits) RISC-V: hwprobe: Fix vDSO SIGSEGV riscv: configs: defconfig: Enable configs required for RZ/Five SoC riscv: errata: prefix T-Head mnemonics with th. riscv: put interrupt entries into .irqentry.text riscv: mm: Update the comment of CONFIG_PAGE_OFFSET riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause riscv/mm: Fix the comment for swap pte format RISC-V: clarify the QEMU workaround in ISA parser riscv: correct pt_level name via pgtable_l5/4_enabled RISC-V: Provide pgtable_l5_enabled on rv32 clocksource: timer-riscv: Increase rating of clock_event_device for Sstc clocksource: timer-riscv: Don't enable/disable timer interrupt lkdtm: Fix CFI_BACKWARD on RISC-V riscv: Use separate IRQ shadow call stacks riscv: Implement Shadow Call Stack riscv: Move global pointer loading to a macro riscv: Deduplicate IRQ stack switching riscv: VMAP_STACK overflow detection thread-safe RISC-V: cacheflush: Initialize CBO variables on ACPI systems RISC-V: ACPI: RHCT: Add function to get CBO block sizes ...
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
|
/*
|
|
* Copyright 2023 Rivos, Inc
|
|
*/
|
|
|
|
#ifndef _UAPI_ASM_HWPROBE_H
|
|
#define _UAPI_ASM_HWPROBE_H
|
|
|
|
#include <linux/types.h>
|
|
|
|
/*
|
|
* Interface for probing hardware capabilities from userspace, see
|
|
* Documentation/arch/riscv/hwprobe.rst for more information.
|
|
*/
|
|
struct riscv_hwprobe {
|
|
__s64 key;
|
|
__u64 value;
|
|
};
|
|
|
|
#define RISCV_HWPROBE_KEY_MVENDORID 0
|
|
#define RISCV_HWPROBE_KEY_MARCHID 1
|
|
#define RISCV_HWPROBE_KEY_MIMPID 2
|
|
#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
|
|
#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
|
|
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
|
|
#define RISCV_HWPROBE_IMA_FD (1 << 0)
|
|
#define RISCV_HWPROBE_IMA_C (1 << 1)
|
|
#define RISCV_HWPROBE_IMA_V (1 << 2)
|
|
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
|
|
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
|
|
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
|
|
#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
|
|
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
|
|
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
|
|
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
|
|
#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
|
|
#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
|
|
#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
|
|
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
|
|
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
|
|
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
|
|
|
|
#endif
|