Commit Graph

118758 Commits

Author SHA1 Message Date
Alex Bennée
69f11e4730 include/exec: fix some copy and paste errors in kdoc
A number of copy and paste kdoc comments are referring to the wrong
definition. Fix those cases.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-30-alex.bennee@linaro.org>
2025-01-17 10:45:38 +00:00
Alex Bennée
64965b4b30 tests/qtest: fix some copy and paste errors in kdoc
A number of copy and paste kdoc comments are referring to the wrong
definition. Fix those cases.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-29-alex.bennee@linaro.org>
2025-01-17 10:45:38 +00:00
Alex Bennée
c08f9d8dec editorconfig: update for perl scripts
We have two types of perl scripts in the tree. The ones from the
kernel are mostly tab based where as scripts we have written ourselves
use 4 space indentation.

Attempt to codify that in our .editorconfig

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-28-alex.bennee@linaro.org>
2025-01-17 10:45:38 +00:00
Alex Bennée
b165ee1916 plugins: fix kdoc annotation
The function is qemu_plugin_mem_get_value()

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-27-alex.bennee@linaro.org>
2025-01-17 10:45:38 +00:00
Pierrick Bouvier
923710b6d5 plugins: enable linking with clang/lld
Windows uses a special mechanism to enable plugins to work (DLL delay
loading). Option for lld is different than ld.

MSYS2 clang based environment use lld by default, so restricting to this
config on Windows is safe, and will avoid false bug reports.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Stefan Weil <sw@weilnetz.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20250110203401.178532-4-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-26-alex.bennee@linaro.org>
2025-01-17 10:45:32 +00:00
Pierrick Bouvier
ecbf3567e2 docs/devel/style: add a section about bitfield, and disallow them for packed structures
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Stefan Weil <sw@weilnetz.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20250110203401.178532-3-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-25-alex.bennee@linaro.org>
2025-01-17 10:45:27 +00:00
Pierrick Bouvier
8f5a4cfc7e win32: remove usage of attribute gcc_struct
This attribute is not recognized by clang.

An investigation has been performed to ensure this attribute has no
effect on layout of structures we use in QEMU [1], so it's safe to
remove now.

In the future, we'll forbid introducing new bitfields in packed struct,
as they are the one potentially impacted by this change.

[1] https://lore.kernel.org/qemu-devel/66c346de-7e20-4831-b3eb-1cda83240af9@linaro.org/

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Tested-by: Stefan Weil <sw@weilnetz.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20250110203401.178532-2-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-24-alex.bennee@linaro.org>
2025-01-17 10:45:13 +00:00
Alex Bennée
27f347e6a1 accel/tcg: also suppress asynchronous IRQs for cpu_io_recompile
While it would be technically correct to allow an IRQ to happen (as
the offending instruction never really completed) it messes up
instrumentation. We already take care to only use memory
instrumentation on the block, we should also suppress IRQs.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Julian Ganz <neither@nut.email>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-23-alex.bennee@linaro.org>
2025-01-17 10:44:59 +00:00
Pierrick Bouvier
db7a06ade1 configure: reenable plugins by default for 32-bit hosts
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-12-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-22-alex.bennee@linaro.org>
2025-01-17 10:44:57 +00:00
Pierrick Bouvier
645bf06012 contrib/plugins/hotpages: fix 32-bit build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-11-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-21-alex.bennee@linaro.org>
2025-01-17 10:44:55 +00:00
Pierrick Bouvier
cab85a63e0 contrib/plugins/hwprofile: fix 32-bit build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-10-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-20-alex.bennee@linaro.org>
2025-01-17 10:44:53 +00:00
Pierrick Bouvier
a5555b2548 contrib/plugins/cflow: fix 32-bit build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-9-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-19-alex.bennee@linaro.org>
2025-01-17 10:44:51 +00:00
Pierrick Bouvier
2fb2aa0bb0 contrib/plugins/hotblocks: fix 32-bit build
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241217224306.2900490-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-18-alex.bennee@linaro.org>
2025-01-17 10:44:49 +00:00
Pierrick Bouvier
aa47f448b5 contrib/plugins/cache: fix 32-bit build
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241217224306.2900490-7-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-17-alex.bennee@linaro.org>
2025-01-17 10:44:46 +00:00
Pierrick Bouvier
03be743f4f contrib/plugins/stoptrigger: fix 32-bit build
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241217224306.2900490-6-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-16-alex.bennee@linaro.org>
2025-01-17 10:44:44 +00:00
Pierrick Bouvier
376bc151c7 tests/tcg/plugins/mem: fix 32-bit build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-5-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-15-alex.bennee@linaro.org>
2025-01-17 10:44:42 +00:00
Pierrick Bouvier
b2a3ebb72c tests/tcg/plugins/syscall: fix 32-bit build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-4-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-14-alex.bennee@linaro.org>
2025-01-17 10:44:38 +00:00
Pierrick Bouvier
d0737068e1 contrib/plugins/howvec: ensure we don't regress if this plugin is extended
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241217224306.2900490-3-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-13-alex.bennee@linaro.org>
2025-01-17 10:44:35 +00:00
Pierrick Bouvier
c7c430065a tests/tcg/plugins/insn: remove unused callback parameter
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-12-alex.bennee@linaro.org>
2025-01-17 10:44:31 +00:00
Alex Bennée
c0e6b8b798 system: propagate Error to gdbserver_start (and other device setups)
This started as a clean-up to properly pass a Error handler to the
gdbserver_start so we could do the right thing for command line and
HMP invocations.

Now that we have cleaned up foreach_device_config_or_exit() in earlier
patches we can further simplify by it by passing &error_fatal instead
of checking the return value. Having a return value is still useful
for HMP though so tweak the return to use a simple bool instead.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-11-alex.bennee@linaro.org>
2025-01-17 10:44:25 +00:00
Alex Bennée
05cdd648a8 system: squash usb_parse into a single function
We don't need to wrap usb_device_add as usb_parse is already gated
with an if (machine_usb(current_machine)) check. Instead just assert
and directly fail if usbdevice_create returns NULL.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-10-alex.bennee@linaro.org>
2025-01-17 10:44:15 +00:00
Alex Bennée
77e911d0c7 system/vl: more error exit into config enumeration code
All of the failures to configure devices will result in QEMU exiting
with an error code. In preparation for passing Error * down the chain
re-name the iterator to foreach_device_config_or_exit and exit using
&error_fatal instead of returning a failure indication.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-9-alex.bennee@linaro.org>
2025-01-17 10:44:05 +00:00
Philippe Mathieu-Daudé
bb0c5be8e9 semihosting/meson: Build config.o and console.o once
config.c and console.c don't use any target specific
headers anymore, move them from specific_ss[] to
system_ss[] so they are built once, but will also be
linked once, removing global symbol clash in a single
QEMU binary.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250103171037.11265-6-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-8-alex.bennee@linaro.org>
2025-01-17 10:44:03 +00:00
Philippe Mathieu-Daudé
5779210656 semihosting/console: Avoid including 'cpu.h'
The CPUState structure is declared in "hw/core/cpu.h",
the EXCP_HALTED definition in "exec/cpu-common.h".
Both headers are indirectly include by "cpu.h". In
order to remove "cpu.h" from "semihosting/console.h",
explicitly include them in console.c, otherwise we'd
get:

  ../semihosting/console.c:88:11: error: incomplete definition of type 'struct CPUState'
     88 |         cs->exception_index = EXCP_HALTED;
        |         ~~^
  ../semihosting/console.c:88:31: error: use of undeclared identifier 'EXCP_HALTED'
     88 |         cs->exception_index = EXCP_HALTED;
        |                               ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250103171037.11265-5-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-7-alex.bennee@linaro.org>
2025-01-17 10:44:00 +00:00
Philippe Mathieu-Daudé
847343cfbf semihosting/arm-compat: Include missing 'cpu.h' header
ARM semihosting implementations in "common-semi-target.h"
must de-reference the target CPUArchState, which is declared
in each target "cpu.h" header. Include it in order to avoid
when refactoring:

  In file included from ../../semihosting/arm-compat-semi.c:169:
  ../target/riscv/common-semi-target.h:16:5: error: use of undeclared identifier 'RISCVCPU'
     16 |     RISCVCPU *cpu = RISCV_CPU(cs);
        |     ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250103171037.11265-4-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-6-alex.bennee@linaro.org>
2025-01-17 10:43:57 +00:00
Philippe Mathieu-Daudé
d2f28a0ce8 semihosting/uaccess: Include missing 'exec/cpu-all.h' header
TLB_INVALID_MASK is defined in "exec/cpu-all.h".
Include it in order to avoid when refactoring:

  ../semihosting/uaccess.c:41:21: error: use of undeclared identifier 'TLB_INVALID_MASK'
     41 |         if (flags & TLB_INVALID_MASK) {
        |                     ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250103171037.11265-3-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-5-alex.bennee@linaro.org>
2025-01-17 10:43:54 +00:00
Philippe Mathieu-Daudé
056c4059e8 semihosting/syscalls: Include missing 'exec/cpu-defs.h' header
target_ulong is defined in each target "cpu-param.h",
itself included by "exec/cpu-defs.h".
Include the latter in order to avoid when refactoring:

  include/semihosting/syscalls.h:26:24: error: unknown type name 'target_ulong'
     26 |                        target_ulong fname, target_ulong fname_len,
        |                        ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250103171037.11265-2-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-4-alex.bennee@linaro.org>
2025-01-17 10:43:51 +00:00
Philippe Mathieu-Daudé
23482ccd6b semihosting/uaccess: Briefly document returned values
Since it is not obvious the get/put_user*() methods
can return an error, add brief docstrings about it.
Also remind to use *unlock_user() when appropriate.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241212115413.42109-1-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-3-alex.bennee@linaro.org>
2025-01-17 10:43:48 +00:00
Alex Bennée
552260aeae semihosting: add guest_error logging for failed opens
This usually indicates the semihosting call was expecting to find
something but didn't.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250116160306.1709518-2-alex.bennee@linaro.org>
2025-01-17 10:43:41 +00:00
Helge Deller
8095f652f2 linux-user: Add missing /proc/cpuinfo fields for sparc
Add some missing fields which may be parsed by userspace applications.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <Z39B1wzNNpndmOxZ@p100>
2025-01-16 20:57:17 -08:00
Richard Henderson
ee97eef290 tcg/riscv: Use BEXTI for single-bit extractions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250102181601.1421059-3-richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
2c4815590f util/cpuinfo-riscv: Detect Zbs
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250102181601.1421059-2-richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
6482e9d2a4 tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}
Make deposit "unconditional" in the sense that the opcode is
always present.  Rely instead on TCG_TARGET_deposit_valid,
now always defined.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
c334de110e tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
Make extract and sextract "unconditional" in the sense
that the opcodes are always present.  Rely instead on
TCG_TARGET_HAS_{s}extract_valid, now always defined.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
41736e7ce1 tcg/tci: Remove assertions for deposit and extract
We already have these assertions during opcode creation.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
d9336b727f tcg/tci: Provide TCG_TARGET_{s}extract_valid
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
3dc7e1db22 tcg/sparc64: Use SRA, SRL for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
42103c4ce7 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
fa65f13555 tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
841e2c5257 tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
94d593941b tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
791d03047b tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract
Accept AND, ext32u, ext32s extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
0c44a4d3b6 tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
802ef65b5f tcg/arm: Add full [US]XT[BH] into {s}extract
The armv6 uxt and sxt opcodes have a 2-bit rotate field
which supports extractions from ofs = {0,8,16,24}.
Special case ofs = 0, len <= 8 as AND.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
936fc0a96e tcg/aarch64: Expand extract with offset 0 with andi
We're about to change canonicalization of masks as extract
instead of and.  Retain the andi expansion here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
42ace08607 tcg/aarch64: Provide TCG_TARGET_{s}extract_valid
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
4bce752c1a tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
ad76017e51 tcg/i386: Handle all 8-bit extensions for i686
When we generalize {s}extract_i32, we'll lose the
specific register constraints on ext8u and ext8s.
It's just as easy to emit a couple of insns instead.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
72912ac736 tcg/mips: Expand bswap unconditionally
We always provide bswap subroutines, whether they are optimized
using mips32r2 when available or not.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00
Richard Henderson
f9af66f6dc tcg: Replace IMPLVEC with TCG_OPF_VECTOR
This is now a direct replacement.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-16 20:57:17 -08:00