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84c0b4a006
Limit GT max frequency to 2600MHz and wait for frequency to reduce before proceeding with a transient flush. This is really only needed for the transient flush: if L2 flush is needed due to 16023588340 then there's no need to do this additional wait since we are already using the bigger hammer. v2: Use generic names, ensure user set max frequency requests wait for flush to complete (Rodrigo) v3: - User requests wait via wait_var_event_timeout (Lucas) - Close races on flush + user requests (Lucas) - Fix xe_guc_pc_remove_flush_freq_limit() being called on last gt rather than root gt (Lucas) v4: - Only apply the freq reducing part if a TDF is needed: L2 flush trumps the need for waiting a lower frequency Fixes:aaa08078e7("drm/xe/bmg: Apply Wa_22019338487") Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://lore.kernel.org/r/20250618-wa-22019338487-v5-4-b888388477f2@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> (cherry picked from commitdeea6a7d6d) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GUC_PC_H_
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#define _XE_GUC_PC_H_
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#include <linux/types.h>
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struct xe_guc_pc;
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enum slpc_gucrc_mode;
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struct drm_printer;
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int xe_guc_pc_init(struct xe_guc_pc *pc);
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int xe_guc_pc_start(struct xe_guc_pc *pc);
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int xe_guc_pc_stop(struct xe_guc_pc *pc);
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int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
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int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
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int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
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void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
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u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
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int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
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u32 xe_guc_pc_get_cur_freq_fw(struct xe_guc_pc *pc);
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u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);
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u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc);
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u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);
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u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc);
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int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq);
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int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq);
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int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq);
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int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq);
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enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc);
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u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc);
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u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
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void xe_guc_pc_init_early(struct xe_guc_pc *pc);
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int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc);
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void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc);
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void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc);
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void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc);
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#endif /* _XE_GUC_PC_H_ */
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