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9e56d026c6
VF's drivers can't modify GGTT PTEs except the range explicitly assigned by the PF driver. To allow hardware enforcement of this requirement, each GGTT PTE has a field with the VF number that identifies which VF can modify that particular GGTT PTE entry. Only PF driver can modify this field and PF driver shall do that before VF drivers will be loaded. Add function to prepare PTEs. Since it will be used only by the PF driver, make it available only for CONFIG_PCI_IOV=y. Bspec: 45015, 52395 Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240415173937.1287-3-michal.wajdeczko@intel.com
38 lines
928 B
C
38 lines
928 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_GTT_DEFS_H_
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#define _XE_GTT_DEFS_H_
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#define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
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#define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
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#define GGTT_PTE_VFID GENMASK_ULL(11, 2)
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#define GUC_GGTT_TOP 0xFEE00000
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#define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62)
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#define XE2_PPGTT_PTE_PAT4 BIT_ULL(61)
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#define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12)
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#define XE_PPGTT_PTE_PAT2 BIT_ULL(7)
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#define XE_PPGTT_PTE_PAT1 BIT_ULL(4)
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#define XE_PPGTT_PTE_PAT0 BIT_ULL(3)
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#define XE_PDE_PS_2M BIT_ULL(7)
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#define XE_PDPE_PS_1G BIT_ULL(7)
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#define XE_PDE_IPS_64K BIT_ULL(11)
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#define XE_GGTT_PTE_DM BIT_ULL(1)
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#define XE_USM_PPGTT_PTE_AE BIT_ULL(10)
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#define XE_PPGTT_PTE_DM BIT_ULL(11)
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#define XE_PDE_64K BIT_ULL(6)
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#define XE_PTE_PS64 BIT_ULL(8)
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#define XE_PTE_NULL BIT_ULL(9)
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#define XE_PAGE_PRESENT BIT_ULL(0)
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#define XE_PAGE_RW BIT_ULL(1)
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#endif
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