linux-loongson/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
Inochi Amaoto 7340c6df49 perf vendor events riscv: add T-HEAD C9xx JSON file
Add JSON file of T-HEAD C9xx series events.

The event idx (raw value) is summary as following:

event id range   | support cpu
 0x01 - 0x2a     |  c906,c910,c920

The event ids are based on the public document of T-HEAD and cover the
c900 series.

These events are the max that c900 series support.  Since T-HEAD let
manufacturers decide whether events are usable, the final support of the
perf events is determined by the pmu node of the soc dtb.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Tested-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Chen Wang <unicorn_wang@outlook.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jisheng Zhang <jszhang@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Wei Fu <wefu@redhat.com>
Cc: linux-riscv@lists.infradead.org
Link: https://lore.kernel.org/r/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2023-11-27 15:53:33 -03:00

81 lines
2.7 KiB
JSON

[
{
"EventName": "LSU_SPEC_FAIL",
"EventCode": "0x0000000a",
"BriefDescription": "LSU speculation fail"
},
{
"EventName": "IDU_RF_PIPE_FAIL",
"EventCode": "0x00000014",
"BriefDescription": "Instruction decode unit launch pipeline failed in RF state"
},
{
"EventName": "IDU_RF_REG_FAIL",
"EventCode": "0x00000015",
"BriefDescription": "Instruction decode unit launch register file fail in RF state"
},
{
"EventName": "IDU_RF_INSTRUCTION",
"EventCode": "0x00000016",
"BriefDescription": "retired instruction count of Instruction decode unit in RF (Register File) stage"
},
{
"EventName": "LSU_4K_STALL",
"EventCode": "0x00000017",
"BriefDescription": "LSU stall times for long distance data access (Over 4K)",
"PublicDescription": "This stall occurs when translate virtual address with page offset over 4k"
},
{
"EventName": "LSU_OTHER_STALL",
"EventCode": "0x00000018",
"BriefDescription": "LSU stall times for other reasons (except the 4k stall)"
},
{
"EventName": "LSU_SQ_OTHER_DIS",
"EventCode": "0x00000019",
"BriefDescription": "LSU store queue discard others"
},
{
"EventName": "LSU_SQ_DATA_DISCARD",
"EventCode": "0x0000001a",
"BriefDescription": "LSU store queue discard data (uops)"
},
{
"EventName": "BRANCH_DIRECTION_MISPREDICTION",
"EventCode": "0x0000001b",
"BriefDescription": "Branch misprediction in BTB"
},
{
"EventName": "BRANCH_DIRECTION_PREDICTION",
"EventCode": "0x0000001c",
"BriefDescription": "All branch prediction in BTB",
"PublicDescription": "This event including both successful prediction and failed prediction in BTB"
},
{
"EventName": "INTERRUPT_ACK_COUNT",
"EventCode": "0x00000023",
"BriefDescription": "acknowledged interrupt count"
},
{
"EventName": "INTERRUPT_OFF_CYCLE",
"EventCode": "0x00000024",
"BriefDescription": "PLIC arbitration time when the interrupt is not responded",
"PublicDescription": "The arbitration time is recorded while meeting any of the following:\n- CPU is M-mode and MIE == 0\n- CPU is S-mode and delegation and SIE == 0\n"
},
{
"EventName": "IFU_STALLED_CYCLE",
"EventCode": "0x00000027",
"BriefDescription": "Number of stall cycles of the instruction fetch unit (IFU)."
},
{
"EventName": "IDU_STALLED_CYCLE",
"EventCode": "0x00000028",
"BriefDescription": "hpcp_backend_stall Number of stall cycles of the instruction decoding unit (IDU) and next-level pipeline unit."
},
{
"EventName": "SYNC_STALL",
"EventCode": "0x00000029",
"BriefDescription": "Sync instruction stall cycle fence/fence.i/sync/sfence"
}
]