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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7340c6df49
Add JSON file of T-HEAD C9xx series events. The event idx (raw value) is summary as following: event id range | support cpu 0x01 - 0x2a | c906,c910,c920 The event ids are based on the public document of T-HEAD and cover the c900 series. These events are the max that c900 series support. Since T-HEAD let manufacturers decide whether events are usable, the final support of the perf events is determined by the pmu node of the soc dtb. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Tested-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Chen Wang <unicorn_wang@outlook.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Jisheng Zhang <jszhang@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Wei Fu <wefu@redhat.com> Cc: linux-riscv@lists.infradead.org Link: https://lore.kernel.org/r/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
68 lines
1.6 KiB
JSON
68 lines
1.6 KiB
JSON
[
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{
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"EventName": "L1_ICACHE_ACCESS",
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"EventCode": "0x00000001",
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"BriefDescription": "L1 instruction cache access"
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},
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{
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"EventName": "L1_ICACHE_MISS",
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"EventCode": "0x00000002",
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"BriefDescription": "L1 instruction cache miss"
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},
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{
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"EventName": "ITLB_MISS",
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"EventCode": "0x00000003",
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"BriefDescription": "I-UTLB miss"
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},
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{
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"EventName": "DTLB_MISS",
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"EventCode": "0x00000004",
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"BriefDescription": "D-UTLB miss"
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},
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{
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"EventName": "JTLB_MISS",
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"EventCode": "0x00000005",
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"BriefDescription": "JTLB miss"
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},
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{
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"EventName": "L1_DCACHE_READ_ACCESS",
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"EventCode": "0x0000000c",
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"BriefDescription": "L1 data cache read access"
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},
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{
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"EventName": "L1_DCACHE_READ_MISS",
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"EventCode": "0x0000000d",
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"BriefDescription": "L1 data cache read miss"
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},
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{
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"EventName": "L1_DCACHE_WRITE_ACCESS",
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"EventCode": "0x0000000e",
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"BriefDescription": "L1 data cache write access"
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},
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{
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"EventName": "L1_DCACHE_WRITE_MISS",
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"EventCode": "0x0000000f",
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"BriefDescription": "L1 data cache write miss"
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},
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{
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"EventName": "LL_CACHE_READ_ACCESS",
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"EventCode": "0x00000010",
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"BriefDescription": "LL Cache read access"
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},
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{
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"EventName": "LL_CACHE_READ_MISS",
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"EventCode": "0x00000011",
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"BriefDescription": "LL Cache read miss"
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},
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{
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"EventName": "LL_CACHE_WRITE_ACCESS",
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"EventCode": "0x00000012",
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"BriefDescription": "LL Cache write access"
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},
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{
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"EventName": "LL_CACHE_WRITE_MISS",
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"EventCode": "0x00000013",
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"BriefDescription": "LL Cache write miss"
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}
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]
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