mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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6dad43bb11
The SiFive Performance P650 core (including the vector-enabled P670 and area-optimized P450/P470 variants) updates the P550 microarchitecture. It brings in the debug, trace, and counter events from newer Bullet cores, and adds new events for iTLB and dTLB multi-hits. All other PMU events are unchanged from the P550 core. Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Ian Rogers <irogers@google.com> Tested-by: Ian Rogers <irogers@google.com> Tested-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250213220341.3215660-8-samuel.holland@sifive.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
63 lines
1.9 KiB
JSON
63 lines
1.9 KiB
JSON
[
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{
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"EventName": "ADDRESSGEN_INTERLOCK",
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"EventCode": "0x101",
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"BriefDescription": "Counts cycles with an address-generation interlock"
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},
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{
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"EventName": "LONGLATENCY_INTERLOCK",
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"EventCode": "0x201",
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"BriefDescription": "Counts cycles with a long-latency interlock"
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},
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{
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"EventName": "CSR_INTERLOCK",
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"EventCode": "0x401",
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"BriefDescription": "Counts cycles with a CSR interlock"
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},
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{
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"EventName": "ICACHE_BLOCKED",
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"EventCode": "0x801",
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"BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
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},
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{
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"EventName": "DCACHE_BLOCKED",
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"EventCode": "0x1001",
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"BriefDescription": "Counts cycles in which the data cache blocked an instruction"
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},
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{
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"EventName": "BRANCH_DIRECTION_MISPREDICTION",
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"EventCode": "0x2001",
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"BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
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},
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{
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"EventName": "BRANCH_TARGET_MISPREDICTION",
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"EventCode": "0x4001",
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"BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
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},
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{
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"EventName": "PIPELINE_FLUSH",
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"EventCode": "0x8001",
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"BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
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},
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{
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"EventName": "REPLAY",
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"EventCode": "0x10001",
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"BriefDescription": "Counts instruction replays"
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},
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{
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"EventName": "INTEGER_MUL_DIV_INTERLOCK",
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"EventCode": "0x20001",
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"BriefDescription": "Counts cycles with a multiply or divide interlock"
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},
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{
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"EventName": "FP_INTERLOCK",
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"EventCode": "0x40001",
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"BriefDescription": "Counts cycles with a floating-point interlock"
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},
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{
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"EventName": "TRACE_STALL",
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"EventCode": "0x80001",
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"BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
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}
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]
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