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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2e3a13d6b7
The SiFive Performance P550 core features an out-of-order microarchitecture which exposes the same PMU events as Bullet, plus events for UTLB hits and PTE cache misses/hits. Add support for specifying these events using symbolic names. Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Ian Rogers <irogers@google.com> Tested-by: Ian Rogers <irogers@google.com> Tested-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250213220341.3215660-7-samuel.holland@sifive.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Symbolic link
1 line
23 B
JSON
Symbolic link
1 line
23 B
JSON
../bullet/firmware.json |