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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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8866a33815
SiFive Bullet microarchitecture cores with mimpid values starting with 0x0d or greater add new PMU events to count TLB miss stall cycles. All other PMU events are unchanged from earlier Bullet cores. Signed-off-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Ian Rogers <irogers@google.com> Tested-by: Ian Rogers <irogers@google.com> Tested-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250213220341.3215660-6-samuel.holland@sifive.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
73 lines
2.2 KiB
JSON
73 lines
2.2 KiB
JSON
[
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{
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"EventName": "ADDRESSGEN_INTERLOCK",
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"EventCode": "0x101",
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"BriefDescription": "Counts cycles with an address-generation interlock"
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},
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{
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"EventName": "LONGLATENCY_INTERLOCK",
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"EventCode": "0x201",
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"BriefDescription": "Counts cycles with a long-latency interlock"
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},
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{
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"EventName": "CSR_INTERLOCK",
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"EventCode": "0x401",
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"BriefDescription": "Counts cycles with a CSR interlock"
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},
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{
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"EventName": "ICACHE_BLOCKED",
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"EventCode": "0x801",
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"BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
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},
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{
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"EventName": "DCACHE_BLOCKED",
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"EventCode": "0x1001",
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"BriefDescription": "Counts cycles in which the data cache blocked an instruction"
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},
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{
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"EventName": "BRANCH_DIRECTION_MISPREDICTION",
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"EventCode": "0x2001",
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"BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
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},
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{
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"EventName": "BRANCH_TARGET_MISPREDICTION",
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"EventCode": "0x4001",
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"BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
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},
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{
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"EventName": "PIPELINE_FLUSH",
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"EventCode": "0x8001",
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"BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
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},
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{
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"EventName": "REPLAY",
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"EventCode": "0x10001",
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"BriefDescription": "Counts instruction replays"
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},
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{
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"EventName": "INTEGER_MUL_DIV_INTERLOCK",
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"EventCode": "0x20001",
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"BriefDescription": "Counts cycles with a multiply or divide interlock"
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},
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{
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"EventName": "FP_INTERLOCK",
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"EventCode": "0x40001",
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"BriefDescription": "Counts cycles with a floating-point interlock"
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},
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{
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"EventName": "TRACE_STALL",
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"EventCode": "0x80001",
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"BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
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},
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{
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"EventName": "ITLB_MISS_STALL",
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"EventCode": "0x100001",
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"BriefDescription": "Counts cycles in which the core pipeline is stalled due to ITLB Miss"
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},
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{
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"EventName": "DTLB_MISS_STALL",
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"EventCode": "0x200001",
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"BriefDescription": "Counts cycles in which the core pipeline is stalled due to DTLB Miss"
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}
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]
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