Eric Lin acaefd6049 perf vendor events riscv: Add SiFive Bullet version 0x07 events ... SiFive Bullet microarchitecture cores with mimpid values starting with 0x07 or greater add new PMU events to support debug, trace, and counter sampling and filtering (Sscofpmf). All other PMU events are unchanged from earlier Bullet cores. Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Ian Rogers <irogers@google.com> Tested-by: Ian Rogers <irogers@google.com> Tested-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250213220341.3215660-5-samuel.holland@sifive.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>		2025-03-10 14:15:38 -07:00
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cycle-and-instruction-count.json
firmware.json
instruction.json
memory.json
microarch.json
watchpoint.json