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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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f5102e31c2
Add the Andes AX45 JSON files that allows specifying symbolic event names for the raw PMU events. Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Atish Patra <atishp@rivosinc.com> Acked-by: Ian Rogers <irogers@google.com> Link: https://lore.kernel.org/r/20240222083946.3977135-11-peterlin@andestech.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
78 lines
1.9 KiB
JSON
78 lines
1.9 KiB
JSON
[
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{
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"EventCode": "0xB1",
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"EventName": "cycle_wait_icache_fill",
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"BriefDescription": "Cycles waiting for ICACHE fill data"
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},
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{
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"EventCode": "0xC1",
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"EventName": "cycle_wait_dcache_fill",
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"BriefDescription": "Cycles waiting for DCACHE fill data"
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},
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{
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"EventCode": "0xD1",
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"EventName": "uncached_ifetch_from_bus",
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"BriefDescription": "Uncached ifetch data access from bus"
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},
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{
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"EventCode": "0xE1",
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"EventName": "uncached_load_from_bus",
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"BriefDescription": "Uncached load data access from bus"
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},
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{
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"EventCode": "0xF1",
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"EventName": "cycle_wait_uncached_ifetch",
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"BriefDescription": "Cycles waiting for uncached ifetch data from bus"
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},
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{
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"EventCode": "0x101",
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"EventName": "cycle_wait_uncached_load",
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"BriefDescription": "Cycles waiting for uncached load data from bus"
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},
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{
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"EventCode": "0x111",
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"EventName": "main_itlb_access",
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"BriefDescription": "Main ITLB access"
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},
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{
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"EventCode": "0x121",
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"EventName": "main_itlb_miss",
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"BriefDescription": "Main ITLB miss"
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},
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{
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"EventCode": "0x131",
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"EventName": "main_dtlb_access",
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"BriefDescription": "Main DTLB access"
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},
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{
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"EventCode": "0x141",
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"EventName": "main_dtlb_miss",
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"BriefDescription": "Main DTLB miss"
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},
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{
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"EventCode": "0x151",
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"EventName": "cycle_wait_itlb_fill",
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"BriefDescription": "Cycles waiting for Main ITLB fill data"
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},
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{
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"EventCode": "0x161",
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"EventName": "pipe_stall_cycle_dtlb_miss",
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"BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
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},
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{
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"EventCode": "0x02",
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"EventName": "mispredict_condition_br",
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"BriefDescription": "Misprediction of conditional branches"
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},
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{
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"EventCode": "0x12",
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"EventName": "mispredict_take_condition_br",
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"BriefDescription": "Misprediction of taken conditional branches"
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},
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{
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"EventCode": "0x22",
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"EventName": "mispredict_target_ret_inst",
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"BriefDescription": "Misprediction of targets of Return instructions"
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}
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]
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