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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
988b28a83b
Add support for adding GPIs to the event FIFO. This is done by adding irq_chip support. Like this, one can use the input gpio_keys driver as a "frontend" device and input handler. As part of this change, we now implement .request() and .free() as we can't blindly consume all available pins as GPIOs (example: some pins can be used for forming a keymap matrix). Also note that the number of pins can now be obtained from the parent, top level device. Hence the 'max_gpio' variable can be removed. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250701-dev-adp5589-fw-v7-15-b1fcfe9e9826@analog.com Signed-off-by: Lee Jones <lee@kernel.org>
227 lines
6.9 KiB
C
227 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Analog Devices ADP5585 I/O expander, PWM controller and keypad controller
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*
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* Copyright 2022 NXP
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* Copyright 2024 Ideas on Board Oy
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*/
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#ifndef __MFD_ADP5585_H_
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#define __MFD_ADP5585_H_
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#include <linux/bits.h>
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#include <linux/notifier.h>
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#define ADP5585_ID 0x00
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#define ADP5585_MAN_ID_VALUE 0x20
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#define ADP5585_MAN_ID_MASK GENMASK(7, 4)
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#define ADP5585_REV_ID_MASK GENMASK(3, 0)
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#define ADP5585_INT_STATUS 0x01
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#define ADP5585_OVRFLOW_INT BIT(2)
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#define ADP5585_EVENT_INT BIT(0)
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#define ADP5585_STATUS 0x02
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#define ADP5585_EC_MASK GENMASK(4, 0)
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#define ADP5585_FIFO_1 0x03
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#define ADP5585_KEV_EV_PRESS_MASK BIT(7)
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#define ADP5585_KEY_EVENT_MASK GENMASK(6, 0)
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#define ADP5585_FIFO_2 0x04
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#define ADP5585_FIFO_3 0x05
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#define ADP5585_FIFO_4 0x06
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#define ADP5585_FIFO_5 0x07
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#define ADP5585_FIFO_6 0x08
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#define ADP5585_FIFO_7 0x09
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#define ADP5585_FIFO_8 0x0a
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#define ADP5585_FIFO_9 0x0b
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#define ADP5585_FIFO_10 0x0c
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#define ADP5585_FIFO_11 0x0d
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#define ADP5585_FIFO_12 0x0e
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#define ADP5585_FIFO_13 0x0f
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#define ADP5585_FIFO_14 0x10
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#define ADP5585_FIFO_15 0x11
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#define ADP5585_FIFO_16 0x12
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#define ADP5585_EV_MAX (ADP5585_FIFO_16 - ADP5585_FIFO_1 + 1)
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#define ADP5585_GPI_INT_STAT_A 0x13
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#define ADP5585_GPI_INT_STAT_B 0x14
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#define ADP5585_GPI_STATUS_A 0x15
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#define ADP5585_GPI_STATUS_B 0x16
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#define ADP5585_RPULL_CONFIG_A 0x17
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#define ADP5585_RPULL_CONFIG_B 0x18
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#define ADP5585_RPULL_CONFIG_C 0x19
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#define ADP5585_RPULL_CONFIG_D 0x1a
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#define ADP5585_Rx_PULL_CFG_PU_300K 0
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#define ADP5585_Rx_PULL_CFG_PD_300K 1
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#define ADP5585_Rx_PULL_CFG_PU_100K 2
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#define ADP5585_Rx_PULL_CFG_DISABLE 3
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#define ADP5585_Rx_PULL_CFG_MASK 3
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#define ADP5585_GPI_INT_LEVEL_A 0x1b
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#define ADP5585_GPI_INT_LEVEL_B 0x1c
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#define ADP5585_GPI_EVENT_EN_A 0x1d
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#define ADP5585_GPI_EVENT_EN_B 0x1e
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#define ADP5585_GPI_INTERRUPT_EN_A 0x1f
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#define ADP5585_GPI_INTERRUPT_EN_B 0x20
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#define ADP5585_DEBOUNCE_DIS_A 0x21
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#define ADP5585_DEBOUNCE_DIS_B 0x22
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#define ADP5585_GPO_DATA_OUT_A 0x23
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#define ADP5585_GPO_DATA_OUT_B 0x24
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#define ADP5585_GPO_OUT_MODE_A 0x25
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#define ADP5585_GPO_OUT_MODE_B 0x26
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#define ADP5585_GPIO_DIRECTION_A 0x27
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#define ADP5585_GPIO_DIRECTION_B 0x28
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#define ADP5585_RESET1_EVENT_A 0x29
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#define ADP5585_RESET_EV_PRESS BIT(7)
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#define ADP5585_RESET1_EVENT_B 0x2a
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#define ADP5585_RESET1_EVENT_C 0x2b
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#define ADP5585_RESET2_EVENT_A 0x2c
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#define ADP5585_RESET2_EVENT_B 0x2d
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#define ADP5585_RESET_CFG 0x2e
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#define ADP5585_PWM_OFFT_LOW 0x2f
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#define ADP5585_PWM_OFFT_HIGH 0x30
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#define ADP5585_PWM_ONT_LOW 0x31
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#define ADP5585_PWM_ONT_HIGH 0x32
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#define ADP5585_PWM_CFG 0x33
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#define ADP5585_PWM_IN_AND BIT(2)
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#define ADP5585_PWM_MODE BIT(1)
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#define ADP5585_PWM_EN BIT(0)
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#define ADP5585_LOGIC_CFG 0x34
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#define ADP5585_LOGIC_FF_CFG 0x35
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#define ADP5585_LOGIC_INT_EVENT_EN 0x36
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#define ADP5585_POLL_PTIME_CFG 0x37
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#define ADP5585_PIN_CONFIG_A 0x38
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#define ADP5585_PIN_CONFIG_B 0x39
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#define ADP5585_PIN_CONFIG_C 0x3a
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#define ADP5585_PULL_SELECT BIT(7)
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#define ADP5585_C4_EXTEND_CFG_GPIO11 (0U << 6)
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#define ADP5585_C4_EXTEND_CFG_RESET2 (1U << 6)
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#define ADP5585_C4_EXTEND_CFG_MASK GENMASK(6, 6)
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#define ADP5585_R4_EXTEND_CFG_GPIO5 (0U << 5)
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#define ADP5585_R4_EXTEND_CFG_RESET1 (1U << 5)
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#define ADP5585_R4_EXTEND_CFG_MASK GENMASK(5, 5)
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#define ADP5585_R3_EXTEND_CFG_GPIO4 (0U << 2)
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#define ADP5585_R3_EXTEND_CFG_LC (1U << 2)
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#define ADP5585_R3_EXTEND_CFG_PWM_OUT (2U << 2)
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#define ADP5585_R3_EXTEND_CFG_MASK GENMASK(3, 2)
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#define ADP5585_R0_EXTEND_CFG_GPIO1 (0U << 0)
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#define ADP5585_R0_EXTEND_CFG_LY (1U << 0)
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#define ADP5585_R0_EXTEND_CFG_MASK GENMASK(0, 0)
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#define ADP5585_GENERAL_CFG 0x3b
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#define ADP5585_OSC_EN BIT(7)
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#define ADP5585_OSC_FREQ_50KHZ (0U << 5)
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#define ADP5585_OSC_FREQ_100KHZ (1U << 5)
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#define ADP5585_OSC_FREQ_200KHZ (2U << 5)
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#define ADP5585_OSC_FREQ_500KHZ (3U << 5)
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#define ADP5585_OSC_FREQ_MASK GENMASK(6, 5)
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#define ADP5585_INT_CFG BIT(1)
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#define ADP5585_RST_CFG BIT(0)
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#define ADP5585_INT_EN 0x3c
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#define ADP5585_OVRFLOW_IEN BIT(2)
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#define ADP5585_EVENT_IEN BIT(0)
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#define ADP5585_MAX_REG ADP5585_INT_EN
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#define ADP5585_PIN_MAX 11
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#define ADP5585_MAX_UNLOCK_TIME_SEC 7
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#define ADP5585_KEY_EVENT_START 1
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#define ADP5585_KEY_EVENT_END 25
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#define ADP5585_GPI_EVENT_START 37
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#define ADP5585_GPI_EVENT_END 47
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#define ADP5585_ROW5_KEY_EVENT_START 1
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#define ADP5585_ROW5_KEY_EVENT_END 30
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#define ADP5585_PWM_OUT 3
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#define ADP5585_RESET1_OUT 4
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#define ADP5585_RESET2_OUT 9
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#define ADP5585_ROW5 5
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/* ADP5589 */
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#define ADP5589_MAN_ID_VALUE 0x10
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#define ADP5589_GPI_STATUS_A 0x16
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#define ADP5589_GPI_STATUS_C 0x18
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#define ADP5589_RPULL_CONFIG_A 0x19
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#define ADP5589_GPI_INT_LEVEL_A 0x1e
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#define ADP5589_GPI_EVENT_EN_A 0x21
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#define ADP5589_DEBOUNCE_DIS_A 0x27
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#define ADP5589_GPO_DATA_OUT_A 0x2a
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#define ADP5589_GPO_OUT_MODE_A 0x2d
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#define ADP5589_GPIO_DIRECTION_A 0x30
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#define ADP5589_UNLOCK1 0x33
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#define ADP5589_UNLOCK_EV_PRESS BIT(7)
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#define ADP5589_UNLOCK_TIMERS 0x36
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#define ADP5589_UNLOCK_TIMER GENMASK(2, 0)
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#define ADP5589_LOCK_CFG 0x37
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#define ADP5589_LOCK_EN BIT(0)
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#define ADP5589_RESET1_EVENT_A 0x38
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#define ADP5589_RESET2_EVENT_A 0x3B
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#define ADP5589_RESET_CFG 0x3D
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#define ADP5585_RESET2_POL BIT(7)
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#define ADP5585_RESET1_POL BIT(6)
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#define ADP5585_RST_PASSTHRU_EN BIT(5)
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#define ADP5585_RESET_TRIG_TIME GENMASK(4, 2)
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#define ADP5585_PULSE_WIDTH GENMASK(1, 0)
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#define ADP5589_PWM_OFFT_LOW 0x3e
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#define ADP5589_PWM_ONT_LOW 0x40
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#define ADP5589_PWM_CFG 0x42
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#define ADP5589_POLL_PTIME_CFG 0x48
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#define ADP5589_PIN_CONFIG_A 0x49
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#define ADP5589_PIN_CONFIG_D 0x4C
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#define ADP5589_GENERAL_CFG 0x4d
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#define ADP5589_INT_EN 0x4e
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#define ADP5589_MAX_REG ADP5589_INT_EN
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#define ADP5589_PIN_MAX 19
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#define ADP5589_KEY_EVENT_START 1
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#define ADP5589_KEY_EVENT_END 88
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#define ADP5589_GPI_EVENT_START 97
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#define ADP5589_GPI_EVENT_END 115
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#define ADP5589_UNLOCK_WILDCARD 127
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#define ADP5589_RESET2_OUT 12
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struct regmap;
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enum adp5585_variant {
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ADP5585_00 = 1,
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ADP5585_01,
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ADP5585_02,
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ADP5585_03,
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ADP5585_04,
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ADP5589_00,
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ADP5589_01,
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ADP5589_02,
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ADP5585_MAX
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};
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struct adp5585_regs {
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unsigned int gen_cfg;
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unsigned int ext_cfg;
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unsigned int int_en;
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unsigned int poll_ptime_cfg;
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unsigned int reset_cfg;
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unsigned int reset1_event_a;
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unsigned int reset2_event_a;
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unsigned int pin_cfg_a;
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};
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struct adp5585_dev {
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struct device *dev;
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struct regmap *regmap;
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const struct adp5585_regs *regs;
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struct blocking_notifier_head event_notifier;
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unsigned long *pin_usage;
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unsigned int n_pins;
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unsigned int reset2_out;
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enum adp5585_variant variant;
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unsigned int id;
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bool has_unlock;
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bool has_pin6;
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int irq;
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unsigned int ev_poll_time;
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unsigned int unlock_time;
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unsigned int unlock_keys[2];
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unsigned int nkeys_unlock;
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unsigned int reset1_keys[3];
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unsigned int nkeys_reset1;
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unsigned int reset2_keys[2];
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unsigned int nkeys_reset2;
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u8 reset_cfg;
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};
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#endif
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