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8aa7306631
Prevent other bits of mailbox power limit from being overwritten with 0.
This issue was due to a missing read and modify of current power limit,
before setting a requested mailbox power limit, which is added in this
patch.
v2:
- Improve commit message. (Anshuman)
v3:
- Rebase.
- Rephrase commit message. (Riana)
- Add read-modify-write variant of xe_hwmon_pcode_write_power_limit()
i.e. xe_hwmon_pcode_rmw_power_limit(). (Badal)
- Use xe_hwmon_pcode_rmw_power_limit() to set mailbox power limits.
- Remove xe_hwmon_pcode_write_power_limit() as all mailbox power limits
writes use xe_hwmon_pcode_rmw_power_limit() only.
v4:
- Use PWR_LIM in place of (PWR_LIM_EN | PWR_LIM_VAL) wherever
applicable. (Riana)
Fixes: 7596d839f6 ("drm/xe/hwmon: Add support to manage power limits though mailbox")
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Link: https://lore.kernel.org/r/20250617120030.612819-1-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_MCHBAR_REGS_H_
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#define _XE_MCHBAR_REGS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* MCHBAR mirror.
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*
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* This mirrors the MCHBAR MMIO space whose location is determined by
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* device 0 function 0's pci config register 0x44 or 0x48 and matches it in
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* every way.
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*/
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#define MCHBAR_MIRROR_BASE_SNB 0x140000
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#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
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#define PKG_TDP GENMASK_ULL(14, 0)
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#define PKG_MIN_PWR GENMASK_ULL(30, 16)
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#define PKG_MAX_PWR GENMASK_ULL(46, 32)
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#define PKG_MAX_WIN GENMASK_ULL(54, 48)
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#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
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#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
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#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
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#define PKG_PWR_UNIT REG_GENMASK(3, 0)
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#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
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#define PKG_TIME_UNIT REG_GENMASK(19, 16)
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#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
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#define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
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#define TEMP_MASK REG_GENMASK(7, 0)
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#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
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#define PWR_LIM_VAL REG_GENMASK(14, 0)
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#define PWR_LIM_EN REG_BIT(15)
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#define PWR_LIM REG_GENMASK(15, 0)
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#define PWR_LIM_TIME REG_GENMASK(23, 17)
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#define PWR_LIM_TIME_X REG_GENMASK(23, 22)
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#define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
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#endif /* _XE_MCHBAR_REGS_H_ */
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