linux-loongson/drivers/gpu/drm/amd/display/dc/hwss/dcn351
Meenakshikumar Somasundaram 8aaeb25327 drm/amd/display: Fix pixel rate divider policy for 1 pixel per cycle config
[Why]
Pixel rate dividor was not programmed correctly for 1 pixel per cycle
configuration for empty tu case.

[How]
Included check for empty tu when pixel rate dividor values were selected.

Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-22 08:51:44 -04:00
..
dcn351_hwseq.c drm/amd/display: Modify power sequence 2024-04-12 00:36:40 -04:00
dcn351_hwseq.h drm/amd/display: Modify power sequence 2024-04-12 00:36:40 -04:00
dcn351_init.c drm/amd/display: Fix pixel rate divider policy for 1 pixel per cycle config 2025-04-22 08:51:44 -04:00
dcn351_init.h
Makefile drm/amd/display: Modify power sequence 2024-04-12 00:36:40 -04:00