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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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707b74c6c2
The name should match the pattern defined in the mmc-controller binding. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202507220336.JhvVLL7k-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202507220215.wVoUMK5B-lkp@intel.com/ Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
312 lines
7.8 KiB
Plaintext
312 lines
7.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright 2023 Mobileye Vision Technologies Ltd.
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*/
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "img,i6500";
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reg = <0>;
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clocks = <&olb EQ5C_CPU_CORE0>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* These reserved memory regions are also defined in bootmanager
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* for configuring inbound translation for BARS, don't change
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* these without syncing with bootmanager
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*/
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shmem0_reserved: shmem@804000000 {
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reg = <0x8 0x04000000 0x0 0x1000000>;
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};
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shmem1_reserved: shmem@805000000 {
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reg = <0x8 0x05000000 0x0 0x1000000>;
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};
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pci0_msi_reserved: pci0-msi@806000000 {
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reg = <0x8 0x06000000 0x0 0x100000>;
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};
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pci1_msi_reserved: pci1-msi@806100000 {
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reg = <0x8 0x06100000 0x0 0x100000>;
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};
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mini_coredump0_reserved: mini-coredump0@806200000 {
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reg = <0x8 0x06200000 0x0 0x100000>;
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};
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mhm_reserved_0: the-mhm-reserved-0@0 {
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reg = <0x8 0x00000000 0x0 0x0000800>;
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};
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nvram@461fe00 {
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compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem";
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reg = <0x0 0x0461fe00 0x0 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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no-map;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eth0_mac: mac@7c {
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reg = <0x7c 0x6>;
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};
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eth1_mac: mac@82 {
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reg = <0x82 0x6>;
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};
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};
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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xtal: xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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};
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pclk: pclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>; /* 250MHz */
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};
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tsu_clk: tsu-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>; /* 125MHz */
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "simple-bus";
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i2c0: i2c@300000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x300000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>; /* Fast mode */
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
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clock-names = "i2cclk", "apb_pclk";
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resets = <&olb 0 13>;
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i2c-transfer-timeout-us = <10000>;
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mobileye,olb = <&olb 0>;
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};
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i2c1: i2c@400000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x400000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>; /* Fast mode */
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
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clock-names = "i2cclk", "apb_pclk";
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resets = <&olb 0 14>;
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i2c-transfer-timeout-us = <10000>;
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mobileye,olb = <&olb 1>;
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};
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i2c2: i2c@500000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x500000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>; /* Fast mode */
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
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clock-names = "i2cclk", "apb_pclk";
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resets = <&olb 0 15>;
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i2c-transfer-timeout-us = <10000>;
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mobileye,olb = <&olb 2>;
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};
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i2c3: i2c@600000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x600000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>; /* Fast mode */
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
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clock-names = "i2cclk", "apb_pclk";
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resets = <&olb 0 16>;
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i2c-transfer-timeout-us = <10000>;
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mobileye,olb = <&olb 3>;
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};
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i2c4: i2c@700000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x700000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>; /* Fast mode */
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
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clock-names = "i2cclk", "apb_pclk";
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resets = <&olb 0 17>;
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i2c-transfer-timeout-us = <10000>;
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mobileye,olb = <&olb 4>;
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};
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uart0: serial@800000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x800000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&olb 0 10>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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uart1: serial@900000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x900000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&olb 0 11>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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};
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uart2: serial@a00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xa00000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&olb 0 12>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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};
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olb: system-controller@e00000 {
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compatible = "mobileye,eyeq5-olb", "syscon";
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reg = <0 0xe00000 0x0 0x400>;
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#reset-cells = <2>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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gic: interrupt-controller@140000 {
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compatible = "mti,gic";
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reg = <0x0 0x140000 0x0 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&olb EQ5C_CPU_CORE0>;
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};
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};
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emmc: mmc@2200000 {
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compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
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reg = <0 0x2200000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&olb EQ5C_PER_EMMC>;
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bus-width = <8>;
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max-frequency = <200000000>;
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mmc-ddr-1_8v;
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sd-uhs-ddr50;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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cdns,phy-input-delay-legacy = <4>;
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cdns,phy-input-delay-mmc-highspeed = <2>;
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cdns,phy-input-delay-mmc-ddr = <3>;
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cdns,phy-dll-delay-sdclk = <32>;
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cdns,phy-dll-delay-sdclk-hsmmc = <32>;
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cdns,phy-dll-delay-strobe = <32>;
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};
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gpio0: gpio@1400000 {
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compatible = "mobileye,eyeq5-gpio";
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reg = <0x0 0x1400000 0x0 0x1000>;
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gpio-bank = <0>;
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ngpios = <29>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&olb 0 0 29>;
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interrupt-controller;
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#interrupt-cells = <2>;
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resets = <&olb 0 26>;
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};
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gpio1: gpio@1500000 {
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compatible = "mobileye,eyeq5-gpio";
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reg = <0x0 0x1500000 0x0 0x1000>;
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gpio-bank = <1>;
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ngpios = <23>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&olb 0 29 23>;
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interrupt-controller;
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#interrupt-cells = <2>;
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resets = <&olb 0 26>;
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};
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};
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};
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#include "eyeq5-pins.dtsi"
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