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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9cc161a450
Refactor J784s4 SoC files to a common file which uses the superset device to allow reuse in j742s2-evm which uses the subset part. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-1-6a7aa2736797@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
173 lines
3.3 KiB
Plaintext
173 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for J784S4 SoC Family
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*
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* TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
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*
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* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include "k3-j784s4-j742s2-common.dtsi"
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/ {
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model = "Texas Instruments K3 J784S4 SoC";
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compatible = "ti,j784s4";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1: cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a72";
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reg = <0x002>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a72";
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reg = <0x003>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a72";
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reg = <0x100>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_1>;
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a72";
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reg = <0x101>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_1>;
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a72";
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reg = <0x102>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_1>;
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a72";
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reg = <0x103>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_1>;
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};
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};
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};
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#include "k3-j784s4-main.dtsi"
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