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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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a947e57796
Add the node for the AUDIO_EXT_REFCLK0 clock output. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618090724.1917731-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
468 lines
12 KiB
Plaintext
468 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree file for the J722S MAIN domain peripherals
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*
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* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy-ti.h>
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/ {
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serdes_refclk: clk-0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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&cbass_main {
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serdes_wiz0: phy@f000000 {
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compatible = "ti,am64-wiz-10g";
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ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
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clock-names = "fck", "core_ref_clk", "ext_ref_clk";
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num-lanes = <1>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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assigned-clocks = <&k3_clks 279 1>;
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assigned-clock-parents = <&k3_clks 279 5>;
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status = "disabled";
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serdes0: serdes@f000000 {
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compatible = "ti,j721e-serdes-10g";
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reg = <0x0f000000 0x00010000>;
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reg-names = "torrent_phy";
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resets = <&serdes_wiz0 0>;
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reset-names = "torrent_reset";
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clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
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clock-names = "refclk", "phy_en_refclk";
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assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
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<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
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assigned-clock-parents = <&k3_clks 279 1>,
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<&k3_clks 279 1>,
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<&k3_clks 279 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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};
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};
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serdes_wiz1: phy@f010000 {
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compatible = "ti,am64-wiz-10g";
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ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
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clock-names = "fck", "core_ref_clk", "ext_ref_clk";
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num-lanes = <1>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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assigned-clocks = <&k3_clks 280 1>;
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assigned-clock-parents = <&k3_clks 280 5>;
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status = "disabled";
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serdes1: serdes@f010000 {
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compatible = "ti,j721e-serdes-10g";
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reg = <0x0f010000 0x00010000>;
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reg-names = "torrent_phy";
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resets = <&serdes_wiz1 0>;
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reset-names = "torrent_reset";
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clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
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clock-names = "refclk", "phy_en_refclk";
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assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
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<&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
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assigned-clock-parents = <&k3_clks 280 1>,
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<&k3_clks 280 1>,
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<&k3_clks 280 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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};
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};
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pcie0_rc: pcie@f102000 {
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compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
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reg = <0x00 0x0f102000 0x00 0x1000>,
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<0x00 0x0f100000 0x00 0x400>,
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<0x00 0x0d000000 0x00 0x00800000>,
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<0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
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reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
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ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
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<0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
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dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
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device_type = "pci";
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max-link-speed = <3>;
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num-lanes = <1>;
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power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
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clock-names = "fck", "pcie_refclk";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xff>;
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vendor-id = <0x104c>;
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device-id = <0xb010>;
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cdns,no-bar-match-nbits = <64>;
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ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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status = "disabled";
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};
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usbss1: usb@f920000 {
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compatible = "ti,j721e-usb";
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reg = <0x00 0x0f920000 0x00 0x100>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
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clock-names = "ref", "lpm";
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assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
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assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb1: usb@31200000 {
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compatible = "cdns,usb3";
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reg = <0x00 0x31200000 0x00 0x10000>,
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<0x00 0x31210000 0x00 0x10000>,
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<0x00 0x31220000 0x00 0x10000>;
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reg-names = "otg",
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"xhci",
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"dev";
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
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interrupt-names = "host",
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"peripheral",
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"otg";
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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ti_csi2rx1: ticsi2rx@30122000 {
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compatible = "ti,j721e-csi2rx-shim";
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reg = <0x00 0x30122000 0x00 0x1000>;
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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dmas = <&main_bcdma_csi 0 0x5100 0>;
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dma-names = "rx0";
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power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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cdns_csi2rx1: csi-bridge@30121000 {
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compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
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reg = <0x00 0x30121000 0x00 0x1000>;
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clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
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<&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
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clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
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"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
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phys = <&dphy1>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi1_port0: port@0 {
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reg = <0>;
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status = "disabled";
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};
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csi1_port1: port@1 {
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reg = <1>;
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status = "disabled";
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};
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csi1_port2: port@2 {
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reg = <2>;
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status = "disabled";
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};
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csi1_port3: port@3 {
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reg = <3>;
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status = "disabled";
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};
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csi1_port4: port@4 {
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reg = <4>;
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status = "disabled";
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};
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};
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};
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};
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ti_csi2rx2: ticsi2rx@30142000 {
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compatible = "ti,j721e-csi2rx-shim";
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reg = <0x00 0x30142000 0x00 0x1000>;
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
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dmas = <&main_bcdma_csi 0 0x5200 0>;
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dma-names = "rx0";
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status = "disabled";
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cdns_csi2rx2: csi-bridge@30141000 {
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compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
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reg = <0x00 0x30141000 0x00 0x1000>;
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clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
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<&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
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clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
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"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
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phys = <&dphy2>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi2_port0: port@0 {
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reg = <0>;
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status = "disabled";
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};
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csi2_port1: port@1 {
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reg = <1>;
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status = "disabled";
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};
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csi2_port2: port@2 {
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reg = <2>;
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status = "disabled";
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};
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csi2_port3: port@3 {
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reg = <3>;
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status = "disabled";
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};
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csi2_port4: port@4 {
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reg = <4>;
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status = "disabled";
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};
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};
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};
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};
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ti_csi2rx3: ticsi2rx@30162000 {
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compatible = "ti,j721e-csi2rx-shim";
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reg = <0x00 0x30162000 0x00 0x1000>;
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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dmas = <&main_bcdma_csi 0 0x5300 0>;
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dma-names = "rx0";
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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cdns_csi2rx3: csi-bridge@30161000 {
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compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
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reg = <0x00 0x30161000 0x00 0x1000>;
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clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
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<&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
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clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
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"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
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phys = <&dphy3>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi3_port0: port@0 {
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reg = <0>;
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status = "disabled";
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};
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csi3_port1: port@1 {
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reg = <1>;
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status = "disabled";
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};
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csi3_port2: port@2 {
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reg = <2>;
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status = "disabled";
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};
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csi3_port3: port@3 {
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reg = <3>;
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status = "disabled";
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};
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csi3_port4: port@4 {
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reg = <4>;
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status = "disabled";
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};
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};
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};
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};
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dphy1: phy@30130000 {
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compatible = "cdns,dphy-rx";
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reg = <0x00 0x30130000 0x00 0x1100>;
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#phy-cells = <0>;
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power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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dphy2: phy@30150000 {
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compatible = "cdns,dphy-rx";
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reg = <0x00 0x30150000 0x00 0x1100>;
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#phy-cells = <0>;
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power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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dphy3: phy@30170000 {
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compatible = "cdns,dphy-rx";
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reg = <0x00 0x30170000 0x00 0x1100>;
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#phy-cells = <0>;
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power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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main_r5fss0: r5fss@78400000 {
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compatible = "ti,am62-r5fss";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x78400000 0x00 0x78400000 0x8000>,
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<0x78500000 0x00 0x78500000 0x8000>;
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power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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main_r5fss0_core0: r5f@78400000 {
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compatible = "ti,am62-r5f";
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reg = <0x78400000 0x00008000>,
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<0x78500000 0x00008000>;
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reg-names = "atcm", "btcm";
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resets = <&k3_reset 262 1>;
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firmware-name = "j722s-main-r5f0_0-fw";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <262>;
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ti,sci-proc-ids = <0x04 0xff>;
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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};
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};
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c7x_0: dsp@7e000000 {
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compatible = "ti,am62a-c7xv-dsp";
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reg = <0x00 0x7e000000 0x00 0x00200000>;
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reg-names = "l2sram";
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resets = <&k3_reset 208 1>;
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firmware-name = "j722s-c71_0-fw";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <208>;
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ti,sci-proc-ids = <0x30 0xff>;
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status = "disabled";
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};
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c7x_1: dsp@7e200000 {
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compatible = "ti,am62a-c7xv-dsp";
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reg = <0x00 0x7e200000 0x00 0x00200000>;
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reg-names = "l2sram";
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resets = <&k3_reset 268 1>;
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firmware-name = "j722s-c71_1-fw";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <268>;
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ti,sci-proc-ids = <0x31 0xff>;
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status = "disabled";
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};
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};
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&main_bcdma_csi {
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compatible = "ti,j722s-dmss-bcdma-csi";
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reg = <0x00 0x4e230000 0x00 0x100>,
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<0x00 0x4e180000 0x00 0x20000>,
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<0x00 0x4e300000 0x00 0x10000>,
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<0x00 0x4e100000 0x00 0x80000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
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ti,sci-rm-range-tchan = <0x22>;
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};
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/* MCU domain overrides */
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&mcu_r5fss0_core0 {
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firmware-name = "j722s-mcu-r5f0_0-fw";
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};
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/* Wakeup domain overrides */
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&wkup_r5fss0_core0 {
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firmware-name = "j722s-wkup-r5f0_0-fw";
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};
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&main_conf {
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serdes_ln_ctrl: mux-controller@4080 {
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compatible = "reg-mux";
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reg = <0x4080 0x14>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
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<0x10 0x3>; /* SERDES1 lane0 select */
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};
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audio_refclk0: clock@82e0 {
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compatible = "ti,am62-audio-refclk";
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reg = <0x82e0 0x4>;
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clocks = <&k3_clks 157 0>;
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assigned-clocks = <&k3_clks 157 0>;
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assigned-clock-parents = <&k3_clks 157 15>;
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#clock-cells = <0>;
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};
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audio_refclk1: clock@82e4 {
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compatible = "ti,am62-audio-refclk";
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reg = <0x82e4 0x4>;
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clocks = <&k3_clks 157 18>;
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assigned-clocks = <&k3_clks 157 18>;
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assigned-clock-parents = <&k3_clks 157 33>;
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#clock-cells = <0>;
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};
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};
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&wkup_conf {
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pcie0_ctrl: pcie0-ctrl@4070 {
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compatible = "ti,j784s4-pcie-ctrl", "syscon";
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reg = <0x4070 0x4>;
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};
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};
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&oc_sram {
|
|
reg = <0x00 0x70000000 0x00 0x40000>;
|
|
ranges = <0x00 0x00 0x70000000 0x40000>;
|
|
};
|
|
|
|
&inta_main_dmss {
|
|
ti,interrupt-ranges = <7 71 21>;
|
|
};
|
|
|
|
&main_gpio0 {
|
|
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
|
|
<&main_pmx0 70 72 17>;
|
|
ti,ngpio = <87>;
|
|
};
|
|
|
|
&main_gpio1 {
|
|
gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
|
|
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
|
|
gpio-reserved-ranges = <0 7>, <32 10>;
|
|
ti,ngpio = <73>;
|
|
};
|