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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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111f6dac6c
Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de> Cc: Jerome Neanne <jneanne@baylibre.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
134 lines
3.0 KiB
Plaintext
134 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
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* J721E board.
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*
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* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/phy/phy-cadence.h>
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#include "k3-pinctrl.h"
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#include "k3-serdes.h"
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&{/} {
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aliases {
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ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
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ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
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ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
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ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
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};
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};
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&cpsw0 {
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status = "okay";
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};
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&cpsw0_port1 {
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status = "okay";
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phy-handle = <&cpsw9g_phy0>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 1>;
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};
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&cpsw0_port2 {
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status = "okay";
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phy-handle = <&cpsw9g_phy1>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 2>;
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};
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&cpsw0_port3 {
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status = "okay";
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phy-handle = <&cpsw9g_phy2>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 3>;
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};
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&cpsw0_port4 {
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status = "okay";
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phy-handle = <&cpsw9g_phy3>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 4>;
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};
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&cpsw9g_mdio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mdio0_pins_default>;
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reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
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reset-post-delay-us = <120000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw9g_phy0: ethernet-phy@17 {
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reg = <17>;
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};
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cpsw9g_phy1: ethernet-phy@16 {
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reg = <16>;
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};
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cpsw9g_phy2: ethernet-phy@18 {
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reg = <18>;
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};
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cpsw9g_phy3: ethernet-phy@19 {
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reg = <19>;
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};
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};
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&exp2 {
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qsgmii-line-hog {
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gpio-hog;
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gpios = <16 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "qsgmii-pwrdn-line";
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};
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};
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&main_pmx0 {
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mdio0_pins_default: mdio0-default-pins {
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pinctrl-single,pins = <
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J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
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J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
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>;
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};
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};
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&serdes_ln_ctrl {
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idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
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<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
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<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
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<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
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<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
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<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
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};
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&serdes_wiz0 {
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status = "okay";
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};
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&serdes0 {
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status = "okay";
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assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
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assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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serdes0_qsgmii_link: phy@1 {
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reg = <1>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_QSGMII>;
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resets = <&serdes_wiz0 2>;
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};
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};
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