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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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df2210b2da
This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe nodes. Signed-off-by: Andrew Davis <afd@ti.com> [j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250402113201.151195-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
54 lines
1.4 KiB
Plaintext
54 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
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* J7 common processor board.
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*
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* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
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*
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* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/*
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* Since Root Complex and Endpoint modes are mutually exclusive
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* disable Root Complex mode.
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*/
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&pcie0_rc {
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status = "disabled";
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};
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&cbass_main {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic500>;
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pcie0_ep: pcie-ep@2900000 {
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compatible = "ti,j721e-pcie-ep";
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reg = <0x00 0x02900000 0x00 0x1000>,
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<0x00 0x02907000 0x00 0x400>,
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<0x00 0x0d000000 0x00 0x00800000>,
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<0x00 0x10000000 0x00 0x08000000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "mem";
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
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ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
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max-link-speed = <3>;
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num-lanes = <1>;
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power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 239 1>;
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clock-names = "fck";
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max-functions = /bits/ 8 <6>;
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max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
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dma-coherent;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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};
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};
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