mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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dba27d026f
To allow firmware to pick up all DTs from here, move the overlays that are normally applied during DT fixup to the kernel source as well. Hook then into the build nevertheless to ensure that regular checks are performed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/91f8b825467651ebd51a4051f153ab136eeb1849.1724830741.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
48 lines
1006 B
Plaintext
48 lines
1006 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
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* Copyright (c) Siemens AG, 2022-2024
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*
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* Authors:
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* Chao Zeng <chao.zeng@siemens.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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&serdes0 {
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assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie1_rc {
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pinctrl-names = "default";
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pinctrl-0 = <&minipcie_pins_default>;
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num-lanes = <1>;
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phys = <&serdes1 PHY_TYPE_PCIE 0>;
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phy-names = "pcie-phy0";
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reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dwc3_0 {
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assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
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<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
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phys = <&serdes0 PHY_TYPE_USB3 0>;
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phy-names = "usb3-phy";
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};
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&usb0 {
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maximum-speed = "super-speed";
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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};
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