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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e0133f883c
The PG1 A variant of the iot2050 series has been identified which partially lacks support for lock-step mode. This implies that all iot2050 boards can't support this mode. As a result, lock-step mode has been disabled across all iot2050 boards for consistency and to avoid potential issues. Signed-off-by: Li Hua Qian <huaqian.li@siemens.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/d1f5f84db7a1597cd29628a0b503e578367b7b40.1724830741.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
36 lines
805 B
Plaintext
36 lines
805 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Siemens AG, 2021-2023
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*
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* Authors:
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* Chao Zeng <chao.zeng@siemens.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* Common bits of the IOT2050 Basic and Advanced variants, PG2
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*/
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&main_pmx0 {
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cp2102n_reset_pin_default: cp2102n-reset-default-pins {
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pinctrl-single,pins = <
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/* (AF12) GPIO1_24, used as cp2102 reset */
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AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
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>;
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};
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};
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&main_gpio1 {
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pinctrl-names = "default";
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pinctrl-0 =
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<&main_pcie_enable_pins_default>,
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<&cp2102n_reset_pin_default>;
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gpio-line-names =
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "CP2102N-RESET";
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};
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&dss {
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/* Workaround needed to get DP clock of 154Mhz */
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assigned-clocks = <&k3_clks 67 0>;
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};
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