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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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fdf47b3a37
External interfaces should be disabled at the SoC DTSI level, since the node is incomplete. Disable Ethernet switch and ports in SoC DTSI and enable them in the board DTS. If the board DTS includes a SoM DTSI that completes the node description, enable the Ethernet switch and ports in SoM DTSI. Reflect this change in SoM DTSIs by removing ethernet port disable. Signed-off-by: Logan Bristol <logan.bristol@utexas.edu> Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Acked-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20240809135753.1186-1-logan.bristol@utexas.edu Signed-off-by: Nishanth Menon <nm@ti.com>
593 lines
17 KiB
Plaintext
593 lines
17 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
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*
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*/
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#include <dt-bindings/net/ti-dp83869.h>
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/ {
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model = "SolidRun AM642 SoM";
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compatible = "solidrun,am642-sr-som", "ti,am642";
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aliases {
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ethernet0 = &cpsw_port1;
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ethernet1 = &icssg1_emac0;
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ethernet2 = &icssg1_emac1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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serial2 = &main_uart0;
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};
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chosen {
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/* SoC default UART console */
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stdout-path = "serial2:115200n8";
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};
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/* PRU Ethernet Controller */
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ethernet {
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compatible = "ti,am642-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
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sram = <&oc_sram>;
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ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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/* configure internal pinmux for mii mode */
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ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
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ti,mii-g-rt = <&icssg1_mii_g_rt>;
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ti,mii-rt = <&icssg1_mii_rt>;
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ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
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/*
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* Configure icssg interrupt controller to map pru-internal
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* interrupts 8/9 via channels 0/1 to host interrupts 0/1.
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*
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* For details see interrupt controller documentation:
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* Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
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*/
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interrupt-parent = <&icssg1_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
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<&main_pktdma 0xc201 15>, /* egress slice 0 */
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<&main_pktdma 0xc202 15>, /* egress slice 0 */
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<&main_pktdma 0xc203 15>, /* egress slice 0 */
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<&main_pktdma 0xc204 15>, /* egress slice 1 */
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<&main_pktdma 0xc205 15>, /* egress slice 1 */
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<&main_pktdma 0xc206 15>, /* egress slice 1 */
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<&main_pktdma 0xc207 15>, /* egress slice 1 */
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<&main_pktdma 0x4200 15>, /* ingress slice 0 */
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<&main_pktdma 0x4201 15>; /* ingress slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg1_emac0: port@0 {
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reg = <0>;
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ti,syscon-rgmii-delay = <&main_conf 0x4110>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-handle = <ðernet_phy2>;
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phy-mode = "rgmii-id";
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};
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icssg1_emac1: port@1 {
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reg = <1>;
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ti,syscon-rgmii-delay = <&main_conf 0x4114>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-handle = <ðernet_phy1>;
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phy-mode = "rgmii-id";
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};
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};
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};
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/* DDR16SS0:
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* - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space
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* - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space
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*/
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memory@80000000 {
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000001 0x80000000>;
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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};
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vdd_mmc0: regulator-vdd-mmc0 {
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compatible = "regulator-fixed";
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regulator-name = "vdd-mmc0";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&cpsw3g {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_default_pins>;
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status = "okay";
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};
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&cpsw3g_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio0_default_pins>;
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status = "okay";
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ethernet_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id2000.a0f1";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_phy0_default_pins>;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
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/*
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* Disable interrupts because ISR never clears 0x0040
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*
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* interrupt-parent = <&main_gpio1>;
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* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
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*/
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/*
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* Disable HW Reset because clock signal is daisy-chained
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*
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* reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
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* reset-assert-us = <1>;
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* reset-deassert-us = <30>;
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*/
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy0>;
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status = "okay";
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};
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&icssg1_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&pru1_mdio0_default_pins>;
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status = "okay";
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ethernet_phy1: ethernet-phy@3 {
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compatible = "ethernet-phy-id2000.a0f1";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_phy1_default_pins>;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
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/*
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* Disable interrupts because ISR never clears 0x0040
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*
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* interrupt-parent = <&main_gpio1>;
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* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
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*/
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/*
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* Disable HW Reset because clock signal is daisy-chained
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*
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* reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
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* reset-assert-us = <1>;
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* reset-deassert-us = <30>;
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*/
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};
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ethernet_phy2: ethernet-phy@f {
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compatible = "ethernet-phy-id2000.a0f1";
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reg = <0xf>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_phy2_default_pins>;
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ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
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/*
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* Disable interrupts because ISR never clears 0x0040
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*
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* interrupt-parent = <&main_gpio1>;
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* interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
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*/
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/*
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* Disable HW Reset because clock signal is daisy-chained
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*
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* reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
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* reset-assert-us = <1>;
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* reset-deassert-us = <30>;
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*/
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};
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};
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&mailbox0_cluster2 {
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status = "okay";
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 2>;
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ti,mbox-tx = <1 0 2>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 2>;
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ti,mbox-tx = <3 0 2>;
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};
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};
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&mailbox0_cluster4 {
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status = "okay";
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 2>;
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ti,mbox-tx = <1 0 2>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 2>;
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ti,mbox-tx = <3 0 2>;
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};
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_default_pins>;
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status = "okay";
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som_eeprom: eeprom@50 {
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compatible = "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&main_pmx0 {
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/* hog global functions */
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_phy_default_pins>;
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ethernet_phy_default_pins: ethernet-phy-default-pins {
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pinctrl-single,pins = <
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/* interrupt / power-down, external pull-up on SoM */
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AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */
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>;
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};
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ethernet_phy0_default_pins: ethernet-phy0-default-pins {
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pinctrl-single,pins = <
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/* reset */
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AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
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/* reference clock */
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AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
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>;
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};
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ethernet_phy1_default_pins: ethernet-phy1-default-pins {
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pinctrl-single,pins = <
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/* reset */
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AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
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/* led0, external pull-down on SoM */
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AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */
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/* led1/rxer */
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AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */
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>;
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};
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ethernet_phy2_default_pins: ethernet-phy2-default-pins {
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pinctrl-single,pins = <
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/* reset */
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AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
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/* led0, external pull-down on SoM */
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AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */
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/* led1/rxer */
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AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */
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>;
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};
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main_i2c0_default_pins: main-i2c0-default-pins {
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pinctrl-single,pins = <
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/* external pull-up on SoM */
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AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */
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AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */
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>;
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};
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/*
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* main_mmc0_default_pins: main-mmc0-default-pins
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*
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* MMC0_CMD: no padconfig
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* MMC0_CLK: no padconfig, external pull-up on SoM
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* MMC0_DAT0: no padconfig
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* MMC0_DAT1: no padconfig
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* MMC0_DAT2: no padconfig
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* MMC0_DAT3: no padconfig
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* MMC0_DAT4: no padconfig
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* MMC0_DAT5: no padconfig
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* MMC0_DAT6: no padconfig
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* MMC0_DAT7: no padconfig
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* MMC0_DS: no padconfig, external pull-down on SoM
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*/
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main_mmc1_default_pins: main-mmc1-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
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AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */
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AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */
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AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */
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AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */
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AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */
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/* external pull-down on SoM & Carrier */
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AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */
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AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */
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>;
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};
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main_uart0_default_pins: main-uart0-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */
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AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */
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>;
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};
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mdio0_default_pins: mdio0-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */
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>;
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};
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ospi0_default_pins: ospi0-default-pins {
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pinctrl-single,pins = <
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/* external pull-down on SoM */
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AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */
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AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */
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/* external pull-up on SoM */
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AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */
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AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */
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AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */
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AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */
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AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */
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AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */
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AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */
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AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */
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AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */
|
|
>;
|
|
};
|
|
|
|
ospi0_flash0_default_pins: ospi0-flash0-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */
|
|
AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */
|
|
>;
|
|
};
|
|
|
|
pru1_mdio0_default_pins: pru1-mdio0-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */
|
|
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */
|
|
>;
|
|
};
|
|
|
|
pru_rgmii1_default_pins: pru-rgmii1-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
|
|
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
|
|
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
|
|
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
|
|
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
|
|
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
|
|
AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
|
|
AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
|
|
AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
|
|
AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
|
|
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
|
|
AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
|
|
>;
|
|
};
|
|
|
|
pru_rgmii2_default_pins: pru-rgmii2-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */
|
|
AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */
|
|
AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */
|
|
AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */
|
|
AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */
|
|
AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
|
AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */
|
|
AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */
|
|
AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */
|
|
AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */
|
|
AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */
|
|
AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
|
>;
|
|
};
|
|
|
|
rgmii1_default_pins: rgmii1-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */
|
|
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */
|
|
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */
|
|
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */
|
|
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */
|
|
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
|
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */
|
|
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */
|
|
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */
|
|
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */
|
|
AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */
|
|
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
|
>;
|
|
};
|
|
|
|
usb0_default_pins: usb0-default-pins {
|
|
pinctrl-single,pins = <
|
|
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&main_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
|
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
|
<&main_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
|
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
|
<&main_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core0 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
|
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
|
<&main_r5fss1_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core1 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
|
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
|
<&main_r5fss1_core1_memory_region>;
|
|
};
|
|
|
|
/* SoC default UART console */
|
|
&main_uart0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_uart0_default_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&ospi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ospi0_default_pins>;
|
|
num-cs = <1>;
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ospi0_flash0_default_pins>;
|
|
spi-tx-bus-width = <8>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-max-frequency = <200000000>;
|
|
cdns,tshsl-ns = <50>;
|
|
cdns,tsd2d-ns = <50>;
|
|
cdns,tchsh-ns = <4>;
|
|
cdns,tslch-ns = <4>;
|
|
cdns,read-delay = <0>;
|
|
interrupt-parent = <&main_gpio0>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
|
|
reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
&sdhci0 {
|
|
/* mmc0 pins have no padconfig */
|
|
bus-width = <8>;
|
|
ti,driver-strength-ohm = <50>;
|
|
disable-wp;
|
|
non-removable;
|
|
cap-mmc-hw-reset;
|
|
no-sd;
|
|
/*
|
|
* MMC controller supports switching between 1.8V and 3.3V signalling.
|
|
* However MMC0 (unlike MMC1) does not integrate an LDO.
|
|
* Explicitly link a regulator node for indicating to the driver which
|
|
* voltages are actually usable.
|
|
*/
|
|
vqmmc-supply = <&vdd_mmc0>;
|
|
status = "okay";
|
|
};
|
|
|
|
/*
|
|
* microSD is on carrier - however since SoC can boot from it,
|
|
* configure it just in case.
|
|
*/
|
|
&sdhci1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_mmc1_default_pins>;
|
|
bus-width = <4>;
|
|
ti,driver-strength-ohm = <50>;
|
|
disable-wp;
|
|
status = "okay";
|
|
};
|
|
|
|
/*
|
|
* USB settings are a carrier choice - however since SoC can boot from it,
|
|
* configure as USB-2.0 OTG here, keeping USB-3 serdes disabled.
|
|
*/
|
|
&usb0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb0_default_pins>;
|
|
dr_mode = "otg";
|
|
maximum-speed = "high-speed";
|
|
};
|
|
|
|
&usbss0 {
|
|
ti,vbus-divider;
|
|
ti,usb2-only;
|
|
};
|