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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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ae0aba1218
The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Add label name 'mdio_mux_1' for 'mdio-mux-1' node so that the node 'mdio-mux-1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Link: https://lore.kernel.org/r/20240215103036.2825096-4-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
80 lines
2.0 KiB
Plaintext
80 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* DT overlay for enabling 2nd ICSSG1 port on AM642 EVM
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include "k3-pinctrl.h"
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&{/} {
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aliases {
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ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
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};
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mdio-mux-2 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mdio_mux>;
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mdio-parent-bus = <&icssg1_mdio>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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icssg1_phy2: ethernet-phy@3 {
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reg = <3>;
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tx-internal-delay-ps = <250>;
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rx-internal-delay-ps = <2000>;
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};
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};
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};
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};
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&main_pmx0 {
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icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
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AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
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AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
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AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
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AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
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AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
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AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
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AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
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AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
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AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
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>;
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};
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};
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&cpsw3g {
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pinctrl-0 = <&rgmii1_pins_default>;
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};
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&cpsw_port2 {
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status = "disabled";
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};
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&mdio_mux_1 {
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status = "disabled";
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};
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&icssg1_eth {
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pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
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};
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&icssg1_emac1 {
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status = "okay";
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phy-handle = <&icssg1_phy2>;
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phy-mode = "rgmii-id";
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};
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