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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e569152274
The NAND expansion card (PROC143E1) connects over the User/MCU/PRU Expansion port on the am62-lp-sk EVM. The following pins are shared between McASP1 and GPMC-NAND so both cannot work simultaneously. Pin name McASP1 function GPMC function ======== =============== ============= J17 MCASP1_AXR0 GPMC0_WEN P21 MCASP1_AFSX GPMC0_WAIT0 K17 MCASP1_ACLKX GPMC0_BE0N_CLE K20 MCASP1_AXR2 GPMC0_ADVN_ALE The factory default sets the pins for McASP1 use. (i.e. Resistor Array RA1 installed, RA4 not installed). For NAND use, RA1 has to be removed and RA4 must be installed. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-2-caee496eaf42@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
117 lines
3.2 KiB
Plaintext
117 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "k3-pinctrl.h"
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&mcasp1 {
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status = "disabled";
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};
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&main_pmx0 {
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gpmc0_pins_default: gpmc0-pins-default {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
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AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
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AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
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AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
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AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
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AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
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AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
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AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
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AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
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AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
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AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
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AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
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AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
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AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
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AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
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>;
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};
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};
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&elm0 {
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status = "okay";
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};
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&gpmc0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&gpmc0_pins_default>;
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#address-cells = <2>;
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#size-cells = <1>;
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nand@0,0 {
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compatible = "ti,am64-nand";
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reg = <0 0 64>; /* device IO registers */
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interrupt-parent = <&gpmc0>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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ti,nand-xfer-type = "prefetch-polled";
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ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
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ti,elm-id = <&elm0>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <40>;
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gpmc,cs-wr-off-ns = <40>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <25>;
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gpmc,adv-wr-off-ns = <25>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <20>;
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gpmc,oe-on-ns = <3>;
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gpmc,oe-off-ns = <30>;
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gpmc,access-ns = <30>;
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.tiboot3";
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reg = <0x00000000 0x00200000>; /* 2M */
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};
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partition@200000 {
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label = "NAND.tispl";
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reg = <0x00200000 0x00200000>; /* 2M */
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};
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partition@400000 {
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label = "NAND.tiboot3.backup"; /* 2M */
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reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
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};
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partition@600000 {
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label = "NAND.u-boot";
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reg = <0x00600000 0x00400000>; /* 4M */
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};
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partition@a00000 {
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label = "NAND.u-boot-env";
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reg = <0x00a00000 0x00040000>; /* 256K */
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};
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partition@a40000 {
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label = "NAND.u-boot-env.backup";
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reg = <0x00a40000 0x00040000>; /* 256K */
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};
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partition@a80000 {
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label = "NAND.file-system";
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reg = <0x00a80000 0x3f580000>;
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};
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};
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};
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};
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