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574d6c59da
Drive strength macros defined for FSD platform is not reflecting actual names and values as per HW UM. FSD SoC pinctrl has following four levels of drive-strength and their corresponding values: Level-1 <-> 0 Level-2 <-> 1 Level-4 <-> 2 Level-6 <-> 3 The commit684dac402f("arm64: dts: fsd: Add initial pinctrl support") used drive strength macros defined for Exynos4 SoC family. For some IPs the macros values of Exynos4 matched and worked well, but Exynos4 SoC family drive-strength (names and values) is not exactly matching with FSD SoC. Fix the drive strength macros to reflect actual names and values given in FSD HW UM. Fixes:684dac402f("arm64: dts: fsd: Add initial pinctrl support") Signed-off-by: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20221013104024.50179-2-p.rajanbabu@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
34 lines
849 B
C
34 lines
849 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Tesla FSD DTS pinctrl constants
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2022 Linaro Ltd
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* Author: Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#ifndef __DTS_ARM64_TESLA_FSD_PINCTRL_H__
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#define __DTS_ARM64_TESLA_FSD_PINCTRL_H__
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#define FSD_PIN_PULL_NONE 0
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#define FSD_PIN_PULL_DOWN 1
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#define FSD_PIN_PULL_UP 3
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#define FSD_PIN_DRV_LV1 0
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#define FSD_PIN_DRV_LV2 1
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#define FSD_PIN_DRV_LV4 2
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#define FSD_PIN_DRV_LV6 3
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#define FSD_PIN_FUNC_INPUT 0
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#define FSD_PIN_FUNC_OUTPUT 1
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#define FSD_PIN_FUNC_2 2
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#define FSD_PIN_FUNC_3 3
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#define FSD_PIN_FUNC_4 4
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#define FSD_PIN_FUNC_5 5
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#define FSD_PIN_FUNC_6 6
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#define FSD_PIN_FUNC_EINT 0xf
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#define FSD_PIN_FUNC_F FSD_PIN_FUNC_EINT
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#endif /* __DTS_ARM64_TESLA_FSD_PINCTRL_H__ */
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