mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
885bf52d04
Enable MT25QU512ABB8E12 FLASH connected to XSPI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250704140823.163572-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
441 lines
7.9 KiB
Plaintext
441 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/V2N EVK board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "r9a09g056.dtsi"
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/ {
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model = "Renesas RZ/V2N EVK Board based on r9a09g056n48";
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compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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mmc1 = &sdhi1;
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serial0 = &scif;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x1 0xf8000000>;
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};
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reg_0p8v: regulator-0p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-0.8V";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI1 VqmmC";
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gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios-states = <0>;
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states = <3300000 0>, <1800000 1>;
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};
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/* 32.768kHz crystal */
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x6: x6-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&audio_extal_clk {
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clock-frequency = <22579200>;
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};
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&ehci0 {
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dr_mode = "otg";
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status = "okay";
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};
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ð0 {
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pinctrl-0 = <ð0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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ð1 {
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pinctrl-0 = <ð1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&gpu {
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status = "okay";
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mali-supply = <®_0p8v>;
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};
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&hsusb {
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dr_mode = "otg";
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c6 {
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pinctrl-0 = <&i2c6_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c7 {
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pinctrl-0 = <&i2c7_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c8 {
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pinctrl-0 = <&i2c8_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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raa215300: pmic@12 {
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compatible = "renesas,raa215300";
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reg = <0x12>, <0x6f>;
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reg-names = "main", "rtc";
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clocks = <&x6>;
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clock-names = "xin";
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};
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};
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&mdio0 {
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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rxc-skew-psec = <0>;
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txc-skew-psec = <0>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&mdio1 {
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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rxc-skew-psec = <0>;
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txc-skew-psec = <0>;
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rxdv-skew-psec = <0>;
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txdv-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&ohci0 {
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dr_mode = "otg";
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status = "okay";
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};
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&ostm0 {
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status = "okay";
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};
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&ostm1 {
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status = "okay";
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};
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&ostm2 {
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status = "okay";
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};
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&ostm3 {
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status = "okay";
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};
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&ostm4 {
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status = "okay";
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};
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&ostm5 {
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status = "okay";
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};
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&ostm6 {
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status = "okay";
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};
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&ostm7 {
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status = "okay";
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};
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&pinctrl {
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eth0_pins: eth0 {
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pins = "ET0_TXC_TXCLK";
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output-enable;
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};
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eth1_pins: eth1 {
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pins = "ET1_TXC_TXCLK";
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output-enable;
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};
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i2c0_pins: i2c0 {
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pinmux = <RZV2N_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
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<RZV2N_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
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};
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i2c1_pins: i2c1 {
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pinmux = <RZV2N_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
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<RZV2N_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
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};
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i2c2_pins: i2c2 {
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pinmux = <RZV2N_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
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<RZV2N_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
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};
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i2c3_pins: i2c3 {
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pinmux = <RZV2N_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
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<RZV2N_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
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};
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i2c6_pins: i2c6 {
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pinmux = <RZV2N_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
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<RZV2N_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
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/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
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bias-pull-up;
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};
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i2c7_pins: i2c7 {
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pinmux = <RZV2N_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
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<RZV2N_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
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/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
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bias-pull-up;
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};
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i2c8_pins: i2c8 {
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pinmux = <RZV2N_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
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<RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
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};
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scif_pins: scif {
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pins = "SCIF_TXD", "SCIF_RXD";
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renesas,output-impedance = <1>;
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};
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sd1-pwr-en-hog {
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gpio-hog;
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gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "sd1_pwr_en";
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};
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sdhi1_pins: sd1 {
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sd1-cd {
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pinmux = <RZV2N_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
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};
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sd1-clk {
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pins = "SD1CLK";
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renesas,output-impedance = <3>;
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slew-rate = <0>;
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};
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sd1-dat-cmd {
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pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
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input-enable;
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renesas,output-impedance = <3>;
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slew-rate = <0>;
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};
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};
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usb20_pins: usb20 {
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ovc {
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pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */
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};
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vbus {
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pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */
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};
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};
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xspi_pins: xspi0 {
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ctrl {
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pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
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output-enable;
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};
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io {
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pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
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renesas,output-impedance = <3>;
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};
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};
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};
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&qextal_clk {
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clock-frequency = <24000000>;
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};
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&rtxin_clk {
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clock-frequency = <32768>;
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};
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&scif {
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pinctrl-0 = <&scif_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi1 {
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pinctrl-0 = <&sdhi1_pins>;
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pinctrl-1 = <&sdhi1_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vqmmc_sdhi1>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&usb20phyrst {
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status = "okay";
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};
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&usb2_phy0 {
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pinctrl-0 = <&usb20_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&wdt1 {
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status = "okay";
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};
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&xspi {
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pinctrl-0 = <&xspi_pins>;
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pinctrl-names = "default";
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/*
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* MT25QU512ABB8E12 flash chip is capable of running at 166MHz
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* clock frequency. Set the clock frequency to the maximum 133MHz
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* supported by the RZ/V2N SoC.
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*/
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assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
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assigned-clock-rates = <133333334>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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vcc-supply = <®_1p8v>;
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m25p,fast-read;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x00000000 0x00060000>;
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};
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partition@60000 {
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label = "fip";
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reg = <0x00060000 0x1fa0000>;
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};
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partition@2000000 {
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label = "user";
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reg = <0x2000000 0x2000000>;
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};
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};
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};
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};
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