mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 14:13:39 +00:00
02e95521f3
All ISP instances on V3U have both a channel select and core function block, describe the core region in addition to the existing cs region. The interrupt number already described intended to reflect the cs function but did incorrectly describe the core block. This was not noticed until now as the driver do not make use of the interrupt for the cs block. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250423163113.2961049-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3098 lines
76 KiB
Plaintext
3098 lines
76 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the R-Car V3U (R8A779A0) SoC
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a779a0-sysc.h>
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/ {
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compatible = "renesas,r8a779a0";
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#address-cells = <2>;
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#size-cells = <2>;
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a76_0: cpu@0 {
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compatible = "arm,cortex-a76";
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reg = <0>;
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device_type = "cpu";
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power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
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next-level-cache = <&L3_CA76_0>;
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clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>;
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};
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L3_CA76_0: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A779A0_PD_A2E0D0>;
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cache-unified;
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cache-level = <3>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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bootph-all;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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bootph-all;
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};
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pmu_a76 {
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compatible = "arm,cortex-a76-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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bootph-all;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a779a0-wdt",
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"renesas,rcar-gen4-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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status = "disabled";
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};
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pfc: pinctrl@e6050000 {
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compatible = "renesas,pfc-r8a779a0";
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reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
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<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
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<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
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<0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
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<0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
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bootph-all;
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};
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gpio0: gpio@e6058180 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058180 0 0x54>;
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interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 0 28>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@e6050180 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050180 0 0x54>;
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interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 32 31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@e6050980 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050980 0 0x54>;
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interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 64 25>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@e6058980 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058980 0 0x54>;
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interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 96 17>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@e6060180 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060180 0 0x54>;
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interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 128 27>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@e6060980 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060980 0 0x54>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 160 21>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@e6068180 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6068180 0 0x54>;
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interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 918>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 918>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 192 21>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio7: gpio@e6068980 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6068980 0 0x54>;
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interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 918>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 918>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 224 21>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio8: gpio@e6069180 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6069180 0 0x54>;
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interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 918>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 918>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 256 21>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio9: gpio@e6069980 {
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compatible = "renesas,gpio-r8a779a0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6069980 0 0x54>;
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interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 918>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 918>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 288 21>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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fuse: fuse@e6078800 {
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compatible = "renesas,r8a779a0-efuse";
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reg = <0 0xe6078800 0 0x100>;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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};
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cmt0: timer@e60f0000 {
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compatible = "renesas,r8a779a0-cmt0",
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"renesas,rcar-gen4-cmt0";
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reg = <0 0xe60f0000 0 0x1004>;
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interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 910>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a779a0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 911>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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status = "disabled";
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};
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cmt2: timer@e6140000 {
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compatible = "renesas,r8a779a0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6140000 0 0x1004>;
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interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 912>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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status = "disabled";
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};
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cmt3: timer@e6148000 {
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compatible = "renesas,r8a779a0-cmt1",
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"renesas,rcar-gen4-cmt1";
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reg = <0 0xe6148000 0 0x1004>;
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interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 913>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 913>;
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status = "disabled";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a779a0-cpg-mssr";
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reg = <0 0xe6150000 0 0x4000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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bootph-all;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a779a0-rst";
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reg = <0 0xe6160000 0 0x4000>;
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bootph-all;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a779a0-sysc";
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reg = <0 0xe6180000 0 0x4000>;
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#power-domain-cells = <1>;
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};
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tsc: thermal@e6190000 {
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compatible = "renesas,r8a779a0-thermal";
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reg = <0 0xe6190000 0 0x200>,
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<0 0xe6198000 0 0x200>,
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<0 0xe61a0000 0 0x200>,
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<0 0xe61a8000 0 0x200>,
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<0 0xe61b0000 0 0x200>;
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clocks = <&cpg CPG_MOD 919>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 919>;
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#thermal-sensor-cells = <1>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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};
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tmu0: timer@e61e0000 {
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compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
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reg = <0 0xe61e0000 0 0x30>;
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interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tuni0", "tuni1", "tuni2";
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clocks = <&cpg CPG_MOD 713>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 713>;
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status = "disabled";
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};
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tmu1: timer@e6fc0000 {
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compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
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reg = <0 0xe6fc0000 0 0x30>;
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interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
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clocks = <&cpg CPG_MOD 714>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 714>;
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status = "disabled";
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};
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tmu2: timer@e6fd0000 {
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compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
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reg = <0 0xe6fd0000 0 0x30>;
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interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
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clocks = <&cpg CPG_MOD 715>;
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clock-names = "fck";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 715>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu3: timer@e6fe0000 {
|
|
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
|
|
reg = <0 0xe6fe0000 0 0x30>;
|
|
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
|
|
clocks = <&cpg CPG_MOD 716>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu4: timer@ffc00000 {
|
|
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
|
|
reg = <0 0xffc00000 0 0x30>;
|
|
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
|
|
clocks = <&cpg CPG_MOD 717>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 717>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@e6500000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6500000 0 0x40>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 518>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 518>;
|
|
dmas = <&dmac1 0x91>, <&dmac1 0x90>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 519>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 519>;
|
|
dmas = <&dmac1 0x93>, <&dmac1 0x92>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 520>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 520>;
|
|
dmas = <&dmac1 0x95>, <&dmac1 0x94>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 521>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 521>;
|
|
dmas = <&dmac1 0x97>, <&dmac1 0x96>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e66d8000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66d8000 0 0x40>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 522>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 522>;
|
|
dmas = <&dmac1 0x99>, <&dmac1 0x98>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e66e0000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66e0000 0 0x40>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@e66e8000 {
|
|
compatible = "renesas,i2c-r8a779a0",
|
|
"renesas,rcar-gen4-i2c";
|
|
reg = <0 0xe66e8000 0 0x40>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 524>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 524>;
|
|
dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e6540000 {
|
|
compatible = "renesas,hscif-r8a779a0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6540000 0 0x60>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 514>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 514>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e6550000 {
|
|
compatible = "renesas,hscif-r8a779a0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6550000 0 0x60>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 515>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 515>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e6560000 {
|
|
compatible = "renesas,hscif-r8a779a0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe6560000 0 0x60>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 516>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 516>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif3: serial@e66a0000 {
|
|
compatible = "renesas,hscif-r8a779a0",
|
|
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
|
reg = <0 0xe66a0000 0 0x60>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 517>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x37>, <&dmac1 0x36>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 517>;
|
|
status = "disabled";
|
|
};
|
|
|
|
canfd: can@e6660000 {
|
|
compatible = "renesas,r8a779a0-canfd",
|
|
"renesas,rcar-gen4-canfd";
|
|
reg = <0 0xe6660000 0 0x8000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch_int", "g_int";
|
|
clocks = <&cpg CPG_MOD 328>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "fck", "canfd", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>;
|
|
assigned-clock-rates = <80000000>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 328>;
|
|
status = "disabled";
|
|
|
|
channel0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel3 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel4 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel5 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel6 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel7 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
avb0: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6800000 0 0x1000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 211>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb1: ethernet@e6810000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6810000 0 0x1000>;
|
|
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 212>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 212>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb2: ethernet@e6820000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6820000 0 0x1000>;
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 213>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 213>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb3: ethernet@e6830000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6830000 0 0x1000>;
|
|
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 214>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 214>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb4: ethernet@e6840000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6840000 0 0x1000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 215>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 215>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb5: ethernet@e6850000 {
|
|
compatible = "renesas,etheravb-r8a779a0",
|
|
"renesas,etheravb-rcar-gen4";
|
|
reg = <0 0xe6850000 0 0x1000>;
|
|
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 216>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 216>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <0>;
|
|
tx-internal-delay-ps = <0>;
|
|
iommus = <&ipmmu_ds1 11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@e6e34000 {
|
|
compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e34000 0 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 628>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 628>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a779a0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 702>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 702>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a779a0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a779a0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 704>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x57>, <&dmac1 0x56>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 704>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a779a0",
|
|
"renesas,rcar-gen4-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 705>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x59>, <&dmac1 0x58>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 705>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpu: pwm@e6e80000 {
|
|
compatible = "renesas,tpu-r8a779a0", "renesas,tpu";
|
|
reg = <0 0xe6e80000 0 0x148>;
|
|
interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 718>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 718>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6e90000 0 0x0064>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 618>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 618>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 619>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 619>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 620>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 620>;
|
|
dmas = <&dmac1 0x45>, <&dmac1 0x44>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 621>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 621>;
|
|
dmas = <&dmac1 0x47>, <&dmac1 0x46>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof4: spi@e6c20000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c20000 0 0x0064>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 622>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 622>;
|
|
dmas = <&dmac1 0x49>, <&dmac1 0x48>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof5: spi@e6c28000 {
|
|
compatible = "renesas,msiof-r8a779a0",
|
|
"renesas,rcar-gen4-msiof";
|
|
reg = <0 0xe6c28000 0 0x0064>;
|
|
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin00: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 730>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 730>;
|
|
renesas,id = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin00isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin01: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 731>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 731>;
|
|
renesas,id = <1>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin01isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin01>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin02: video@e6ef2000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 800>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 800>;
|
|
renesas,id = <2>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin02isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin02>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin03: video@e6ef3000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef3000 0 0x1000>;
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 801>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 801>;
|
|
renesas,id = <3>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin03isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin03>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin04: video@e6ef4000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef4000 0 0x1000>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 802>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 802>;
|
|
renesas,id = <4>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin04isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin04>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin05: video@e6ef5000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef5000 0 0x1000>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 803>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 803>;
|
|
renesas,id = <5>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin05isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin05>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin06: video@e6ef6000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef6000 0 0x1000>;
|
|
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 804>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 804>;
|
|
renesas,id = <6>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin06isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin06>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin07: video@e6ef7000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef7000 0 0x1000>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 805>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 805>;
|
|
renesas,id = <7>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin07isp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&isp0vin07>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin08: video@e6ef8000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef8000 0 0x1000>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 806>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 806>;
|
|
renesas,id = <8>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin08isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin08>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin09: video@e6ef9000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ef9000 0 0x1000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 807>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 807>;
|
|
renesas,id = <9>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin09isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin09>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin10: video@e6efa000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6efa000 0 0x1000>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 808>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 808>;
|
|
renesas,id = <10>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin10isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin10>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin11: video@e6efb000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6efb000 0 0x1000>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 809>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 809>;
|
|
renesas,id = <11>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin11isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin11>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin12: video@e6efc000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6efc000 0 0x1000>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 810>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 810>;
|
|
renesas,id = <12>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin12isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin12>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin13: video@e6efd000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6efd000 0 0x1000>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 811>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 811>;
|
|
renesas,id = <13>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin13isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin13>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin14: video@e6efe000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6efe000 0 0x1000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 812>;
|
|
renesas,id = <14>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin14isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin14>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin15: video@e6eff000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6eff000 0 0x1000>;
|
|
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 813>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 813>;
|
|
renesas,id = <15>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin15isp1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&isp1vin15>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin16: video@e6ed0000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 814>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 814>;
|
|
renesas,id = <16>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin16isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin16>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin17: video@e6ed1000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 815>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 815>;
|
|
renesas,id = <17>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin17isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin17>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin18: video@e6ed2000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed2000 0 0x1000>;
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 816>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 816>;
|
|
renesas,id = <18>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin18isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin18>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin19: video@e6ed3000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed3000 0 0x1000>;
|
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 817>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 817>;
|
|
renesas,id = <19>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin19isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin19>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin20: video@e6ed4000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed4000 0 0x1000>;
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 818>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 818>;
|
|
renesas,id = <20>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin20isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin20>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin21: video@e6ed5000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed5000 0 0x1000>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 819>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 819>;
|
|
renesas,id = <21>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin21isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin21>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin22: video@e6ed6000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed6000 0 0x1000>;
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 820>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 820>;
|
|
renesas,id = <22>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin22isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin22>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin23: video@e6ed7000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed7000 0 0x1000>;
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 821>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 821>;
|
|
renesas,id = <23>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin23isp2: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&isp2vin23>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin24: video@e6ed8000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed8000 0 0x1000>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 822>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 822>;
|
|
renesas,id = <24>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin24isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin24>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin25: video@e6ed9000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ed9000 0 0x1000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 823>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 823>;
|
|
renesas,id = <25>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin25isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin25>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin26: video@e6eda000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6eda000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 824>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 824>;
|
|
renesas,id = <26>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin26isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin26>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin27: video@e6edb000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6edb000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 825>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 825>;
|
|
renesas,id = <27>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin27isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin27>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin28: video@e6edc000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6edc000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 826>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 826>;
|
|
renesas,id = <28>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin28isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin28>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin29: video@e6edd000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6edd000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 827>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 827>;
|
|
renesas,id = <29>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin29isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin29>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin30: video@e6ede000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6ede000 0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 828>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 828>;
|
|
renesas,id = <30>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin30isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin30>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vin31: video@e6edf000 {
|
|
compatible = "renesas,vin-r8a779a0",
|
|
"renesas,rcar-gen4-vin";
|
|
reg = <0 0xe6edf000 0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 829>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 829>;
|
|
renesas,id = <31>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
vin31isp3: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&isp3vin31>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dmac1: dma-controller@e7350000 {
|
|
compatible = "renesas,dmac-r8a779a0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7350000 0 0x1000>,
|
|
<0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7", "ch8", "ch9",
|
|
"ch10", "ch11", "ch12", "ch13",
|
|
"ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 709>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 709>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
|
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
|
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
|
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
|
|
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
|
|
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
|
|
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
|
|
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7351000 {
|
|
compatible = "renesas,dmac-r8a779a0",
|
|
"renesas,rcar-gen4-dmac";
|
|
reg = <0 0xe7351000 0 0x1000>,
|
|
<0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3", "ch4",
|
|
"ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 710>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 710>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
|
|
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
|
|
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
|
|
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
|
|
};
|
|
|
|
mmc0: mmc@ee140000 {
|
|
compatible = "renesas,sdhi-r8a779a0",
|
|
"renesas,rcar-gen4-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>;
|
|
clock-names = "core", "clkh";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 706>;
|
|
max-frequency = <200000000>;
|
|
iommus = <&ipmmu_ds0 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpc: spi@ee200000 {
|
|
compatible = "renesas,r8a779a0-rpc-if",
|
|
"renesas,rcar-gen3-rpc-if";
|
|
reg = <0 0xee200000 0 0x200>,
|
|
<0 0x08000000 0 0x04000000>,
|
|
<0 0xee208000 0 0x100>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 629>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 629>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_rt0: iommu@ee480000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xee480000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_rt1: iommu@ee4c0000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xee4c0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ds0: iommu@eed00000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ds1: iommu@eed40000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed40000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ir: iommu@eed80000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeed80000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_A3IR>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vc0: iommu@eedc0000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeedc0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi0: iommu@eee80000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeee80000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi1: iommu@eeec0000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeeec0000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_3dg: iommu@eee00000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeee00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vip0: iommu@eef00000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeef00000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vip1: iommu@eef40000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeef40000 0 0x20000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mm: iommu@eefc0000 {
|
|
compatible = "renesas,ipmmu-r8a779a0",
|
|
"renesas,rcar-gen4-ipmmu-vmsa";
|
|
reg = <0 0xeefc0000 0 0x20000>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@f1000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1000000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x110000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
fcpvd0: fcp@fea10000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea10000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 508>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 508>;
|
|
iommus = <&ipmmu_vi1 6>;
|
|
};
|
|
|
|
fcpvd1: fcp@fea11000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea11000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 509>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 509>;
|
|
iommus = <&ipmmu_vi1 7>;
|
|
};
|
|
|
|
fcpvx0: fcp@fedb0000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfedb0000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 1100>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 1100>;
|
|
iommus = <&ipmmu_vi1 24>;
|
|
};
|
|
|
|
fcpvx1: fcp@fedb8000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfedb8000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 1101>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 1101>;
|
|
iommus = <&ipmmu_vi1 25>;
|
|
};
|
|
|
|
fcpvx2: fcp@fedc0000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfedc0000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 1102>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 1102>;
|
|
iommus = <&ipmmu_vi1 26>;
|
|
};
|
|
|
|
fcpvx3: fcp@fedc8000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfedc8000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 1103>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 1103>;
|
|
iommus = <&ipmmu_vi1 27>;
|
|
};
|
|
|
|
vspd0: vsp@fea20000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea20000 0 0x5000>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 830>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 830>;
|
|
|
|
renesas,fcp = <&fcpvd0>;
|
|
};
|
|
|
|
vspd1: vsp@fea28000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea28000 0 0x5000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 831>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 831>;
|
|
|
|
renesas,fcp = <&fcpvd1>;
|
|
};
|
|
|
|
vspx0: vsp@fedd0000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfedd0000 0 0x8000>;
|
|
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1028>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 1028>;
|
|
|
|
renesas,fcp = <&fcpvx0>;
|
|
};
|
|
|
|
vspx1: vsp@fedd8000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfedd8000 0 0x8000>;
|
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1029>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 1029>;
|
|
|
|
renesas,fcp = <&fcpvx1>;
|
|
};
|
|
|
|
vspx2: vsp@fede0000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfede0000 0 0x8000>;
|
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1030>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 1030>;
|
|
|
|
renesas,fcp = <&fcpvx2>;
|
|
};
|
|
|
|
vspx3: vsp@fede8000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfede8000 0 0x8000>;
|
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 1031>;
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 1031>;
|
|
|
|
renesas,fcp = <&fcpvx3>;
|
|
};
|
|
|
|
csi40: csi2@feaa0000 {
|
|
compatible = "renesas,r8a779a0-csi2";
|
|
reg = <0 0xfeaa0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 331>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 331>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
csi40isp0: endpoint {
|
|
remote-endpoint = <&isp0csi40>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csi41: csi2@feab0000 {
|
|
compatible = "renesas,r8a779a0-csi2";
|
|
reg = <0 0xfeab0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 400>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 400>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
csi41isp1: endpoint {
|
|
remote-endpoint = <&isp1csi41>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csi42: csi2@fed60000 {
|
|
compatible = "renesas,r8a779a0-csi2";
|
|
reg = <0 0xfed60000 0 0x10000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 401>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 401>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
csi42isp2: endpoint {
|
|
remote-endpoint = <&isp2csi42>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csi43: csi2@fed70000 {
|
|
compatible = "renesas,r8a779a0-csi2";
|
|
reg = <0 0xfed70000 0 0x10000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 402>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 402>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
csi43isp3: endpoint {
|
|
remote-endpoint = <&isp3csi43>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a779a0";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 411>;
|
|
clock-names = "du.0";
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
resets = <&cpg 411>;
|
|
reset-names = "du.0";
|
|
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_dsi0: endpoint {
|
|
remote-endpoint = <&dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_dsi1: endpoint {
|
|
remote-endpoint = <&dsi1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
isp0: isp@fed00000 {
|
|
compatible = "renesas,r8a779a0-isp",
|
|
"renesas,rcar-gen4-isp";
|
|
reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
|
|
reg-names = "cs", "core";
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cs", "core";
|
|
clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
|
|
clock-names = "cs", "core";
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 612>, <&cpg 16>;
|
|
reset-names = "cs", "core";
|
|
status = "disabled";
|
|
|
|
renesas,vspx = <&vspx0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
isp0csi40: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&csi40isp0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
isp0vin00: endpoint {
|
|
remote-endpoint = <&vin00isp0>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
isp0vin01: endpoint {
|
|
remote-endpoint = <&vin01isp0>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
isp0vin02: endpoint {
|
|
remote-endpoint = <&vin02isp0>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
isp0vin03: endpoint {
|
|
remote-endpoint = <&vin03isp0>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
isp0vin04: endpoint {
|
|
remote-endpoint = <&vin04isp0>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
isp0vin05: endpoint {
|
|
remote-endpoint = <&vin05isp0>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
isp0vin06: endpoint {
|
|
remote-endpoint = <&vin06isp0>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
isp0vin07: endpoint {
|
|
remote-endpoint = <&vin07isp0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
isp1: isp@fed20000 {
|
|
compatible = "renesas,r8a779a0-isp",
|
|
"renesas,rcar-gen4-isp";
|
|
reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>;
|
|
reg-names = "cs", "core";
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cs", "core";
|
|
clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>;
|
|
clock-names = "cs", "core";
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
|
resets = <&cpg 613>, <&cpg 17>;
|
|
reset-names = "cs", "core";
|
|
status = "disabled";
|
|
|
|
renesas,vspx = <&vspx1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
isp1csi41: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&csi41isp1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
isp1vin08: endpoint {
|
|
remote-endpoint = <&vin08isp1>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
isp1vin09: endpoint {
|
|
remote-endpoint = <&vin09isp1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
isp1vin10: endpoint {
|
|
remote-endpoint = <&vin10isp1>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
isp1vin11: endpoint {
|
|
remote-endpoint = <&vin11isp1>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
isp1vin12: endpoint {
|
|
remote-endpoint = <&vin12isp1>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
isp1vin13: endpoint {
|
|
remote-endpoint = <&vin13isp1>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
isp1vin14: endpoint {
|
|
remote-endpoint = <&vin14isp1>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
isp1vin15: endpoint {
|
|
remote-endpoint = <&vin15isp1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
isp2: isp@fed30000 {
|
|
compatible = "renesas,r8a779a0-isp",
|
|
"renesas,rcar-gen4-isp";
|
|
reg = <0 0xfed30000 0 0x10000>, <0 0xfef00000 0 0x100000>;
|
|
reg-names = "cs", "core";
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cs", "core";
|
|
clocks = <&cpg CPG_MOD 614>, <&cpg CPG_MOD 18>;
|
|
clock-names = "cs", "core";
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 614>, <&cpg 18>;
|
|
reset-names = "cs", "core";
|
|
status = "disabled";
|
|
|
|
renesas,vspx = <&vspx2>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
isp2csi42: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&csi42isp2>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
isp2vin16: endpoint {
|
|
remote-endpoint = <&vin16isp2>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
isp2vin17: endpoint {
|
|
remote-endpoint = <&vin17isp2>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
isp2vin18: endpoint {
|
|
remote-endpoint = <&vin18isp2>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
isp2vin19: endpoint {
|
|
remote-endpoint = <&vin19isp2>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
isp2vin20: endpoint {
|
|
remote-endpoint = <&vin20isp2>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
isp2vin21: endpoint {
|
|
remote-endpoint = <&vin21isp2>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
isp2vin22: endpoint {
|
|
remote-endpoint = <&vin22isp2>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
isp2vin23: endpoint {
|
|
remote-endpoint = <&vin23isp2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
isp3: isp@fed40000 {
|
|
compatible = "renesas,r8a779a0-isp",
|
|
"renesas,rcar-gen4-isp";
|
|
reg = <0 0xfed40000 0 0x10000>, <0 0xfe400000 0 0x100000>;
|
|
reg-names = "cs", "core";
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cs", "core";
|
|
clocks = <&cpg CPG_MOD 615>, <&cpg CPG_MOD 19>;
|
|
clock-names = "cs", "core";
|
|
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
|
resets = <&cpg 615>, <&cpg 19>;
|
|
reset-names = "cs", "core";
|
|
status = "disabled";
|
|
|
|
renesas,vspx = <&vspx3>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
isp3csi43: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&csi43isp3>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
isp3vin24: endpoint {
|
|
remote-endpoint = <&vin24isp3>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
isp3vin25: endpoint {
|
|
remote-endpoint = <&vin25isp3>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
isp3vin26: endpoint {
|
|
remote-endpoint = <&vin26isp3>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
isp3vin27: endpoint {
|
|
remote-endpoint = <&vin27isp3>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
isp3vin28: endpoint {
|
|
remote-endpoint = <&vin28isp3>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
isp3vin29: endpoint {
|
|
remote-endpoint = <&vin29isp3>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
isp3vin30: endpoint {
|
|
remote-endpoint = <&vin30isp3>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
isp3vin31: endpoint {
|
|
remote-endpoint = <&vin31isp3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi0: dsi-encoder@fed80000 {
|
|
compatible = "renesas,r8a779a0-dsi-csi2-tx";
|
|
reg = <0 0xfed80000 0 0x10000>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
clocks = <&cpg CPG_MOD 415>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
|
|
clock-names = "fck", "dsi", "pll";
|
|
resets = <&cpg 415>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dsi0_in: endpoint {
|
|
remote-endpoint = <&du_out_dsi0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi1: dsi-encoder@fed90000 {
|
|
compatible = "renesas,r8a779a0-dsi-csi2-tx";
|
|
reg = <0 0xfed90000 0 0x10000>;
|
|
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
|
clocks = <&cpg CPG_MOD 416>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
|
|
<&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
|
|
clock-names = "fck", "dsi", "pll";
|
|
resets = <&cpg 416>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dsi1_in: endpoint {
|
|
remote-endpoint = <&du_out_dsi1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
sensor1_thermal: sensor1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 0>;
|
|
|
|
trips {
|
|
sensor1_crit: sensor1-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor2_thermal: sensor2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 1>;
|
|
|
|
trips {
|
|
sensor2_crit: sensor2-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor3_thermal: sensor3-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 2>;
|
|
|
|
trips {
|
|
sensor3_crit: sensor3-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor4_thermal: sensor4-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 3>;
|
|
|
|
trips {
|
|
sensor4_crit: sensor4-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor5_thermal: sensor5-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 4>;
|
|
|
|
trips {
|
|
sensor5_crit: sensor5-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
|
|
"hyp-virt";
|
|
};
|
|
};
|