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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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56cf5ad39a
Add DT entries for the sm8650 iris decoder. Since the firmware is required to be signed, only enable on Qualcomm development boards where the firmware is available. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250613-topic-sm8x50-upstream-iris-8650-dt-v4-1-35ea7952f2d2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8244 lines
190 KiB
Plaintext
8244 lines
190 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm8650-camcc.h>
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#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
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#include <dt-bindings/clock/qcom,sm8650-gcc.h>
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#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
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#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
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#include <dt-bindings/clock/qcom,sm8650-videocc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/firmware/qcom,scm.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
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#include <dt-bindings/soc/qcom,gpr.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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bi_tcxo_div2: bi-tcxo-div2-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK_A>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a520";
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reg = <0 0>;
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clocks = <&cpufreq_hw 0>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a520";
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reg = <0 0x100>;
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clocks = <&cpufreq_hw 0>;
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power-domains = <&cpu_pd1>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0 0x200>;
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clocks = <&cpufreq_hw 3>;
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power-domains = <&cpu_pd2>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_200>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 3>;
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operating-points-v2 = <&cpu2_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0 0x300>;
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clocks = <&cpufreq_hw 3>;
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power-domains = <&cpu_pd3>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_300>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 3>;
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operating-points-v2 = <&cpu2_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0 0x400>;
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clocks = <&cpufreq_hw 3>;
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power-domains = <&cpu_pd4>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_400>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 3>;
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operating-points-v2 = <&cpu2_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0 0x500>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd5>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_500>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu5_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_500: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0 0x600>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd6>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_600>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu5_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_600: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-x4";
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reg = <0 0x700>;
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clocks = <&cpufreq_hw 2>;
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power-domains = <&cpu_pd7>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_700>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <588>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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operating-points-v2 = <&cpu7_opp_table>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&epss_l3 MASTER_EPSS_L3_APPS
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&epss_l3 SLAVE_EPSS_L3_SHARED>;
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#cooling-cells = <2>;
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l2_700: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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silver_cpu_sleep_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <550>;
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exit-latency-us = <750>;
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min-residency-us = <6700>;
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local-timer-stop;
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};
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gold_cpu_sleep_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <600>;
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exit-latency-us = <1300>;
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min-residency-us = <8136>;
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local-timer-stop;
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};
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gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-plus-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <500>;
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exit-latency-us = <1350>;
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min-residency-us = <7480>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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cluster_sleep_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <750>;
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exit-latency-us = <2350>;
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min-residency-us = <9144>;
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};
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cluster_sleep_1: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x4100c344>;
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entry-latency-us = <2800>;
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exit-latency-us = <4400>;
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min-residency-us = <10150>;
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};
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};
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};
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ete-0 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu0>;
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out-ports {
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port {
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ete0_out_funnel_ete: endpoint {
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remote-endpoint = <&funnel_ete_in_ete0>;
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};
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};
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};
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};
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ete-1 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu1>;
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out-ports {
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port {
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ete1_out_funnel_ete: endpoint {
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remote-endpoint = <&funnel_ete_in_ete1>;
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};
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};
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};
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};
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ete-2 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu2>;
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out-ports {
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port {
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ete2_out_funnel_ete: endpoint {
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remote-endpoint = <&funnel_ete_in_ete2>;
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};
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};
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};
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};
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ete-3 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu3>;
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out-ports {
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port {
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ete3_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete-4 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
|
|
cpu = <&cpu4>;
|
|
|
|
out-ports {
|
|
port {
|
|
ete4_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete-5 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
|
|
cpu = <&cpu5>;
|
|
|
|
out-ports {
|
|
port {
|
|
ete5_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete-6 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
|
|
cpu = <&cpu6>;
|
|
|
|
out-ports {
|
|
port {
|
|
ete6_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ete-7 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
|
|
cpu = <&cpu7>;
|
|
|
|
out-ports {
|
|
port {
|
|
ete7_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-ete {
|
|
compatible = "arm,coresight-static-funnel";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
funnel_ete_in_ete0: endpoint {
|
|
remote-endpoint = <&ete0_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
funnel_ete_in_ete1: endpoint {
|
|
remote-endpoint = <&ete1_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
funnel_ete_in_ete2: endpoint {
|
|
remote-endpoint = <&ete2_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
|
|
funnel_ete_in_ete3: endpoint {
|
|
remote-endpoint = <&ete3_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
|
|
funnel_ete_in_ete4: endpoint {
|
|
remote-endpoint = <&ete4_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
|
|
funnel_ete_in_ete5: endpoint {
|
|
remote-endpoint = <&ete5_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
|
|
funnel_ete_in_ete6: endpoint {
|
|
remote-endpoint = <&ete6_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
|
|
funnel_ete_in_ete7: endpoint {
|
|
remote-endpoint = <&ete7_out_funnel_ete>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_ete_out_funnel_apss: endpoint {
|
|
remote-endpoint = <&funnel_apss_in_funnel_ete>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
firmware {
|
|
scm: scm {
|
|
compatible = "qcom,scm-sm8650", "qcom,scm";
|
|
qcom,dload-mode = <&tcsr 0x19000>;
|
|
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
};
|
|
};
|
|
|
|
clk_virt: interconnect-0 {
|
|
compatible = "qcom,sm8650-clk-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect-1 {
|
|
compatible = "qcom,sm8650-mc-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
qup_opp_table_100mhz: opp-table-qup100mhz {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-75000000 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
};
|
|
|
|
qup_opp_table_120mhz: opp-table-qup120mhz {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-75000000 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-120000000 {
|
|
opp-hz = /bits/ 64 <120000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
};
|
|
|
|
qup_opp_table_128mhz: opp-table-qup128mhz {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-75000000 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-128000000 {
|
|
opp-hz = /bits/ 64 <128000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
};
|
|
|
|
qup_opp_table_240mhz: opp-table-qup240mhz {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-150000000 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-240000000 {
|
|
opp-hz = /bits/ 64 <240000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
};
|
|
|
|
memory@a0000000 {
|
|
device_type = "memory";
|
|
/* We expect the bootloader to fill in the size */
|
|
reg = <0 0xa0000000 0 0>;
|
|
};
|
|
|
|
cpu0_opp_table: opp-table-cpu0 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-307200000 {
|
|
opp-hz = /bits/ 64 <307200000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-364800000 {
|
|
opp-hz = /bits/ 64 <364800000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-460800000 {
|
|
opp-hz = /bits/ 64 <460800000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
|
|
};
|
|
|
|
opp-556800000 {
|
|
opp-hz = /bits/ 64 <556800000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-672000000 {
|
|
opp-hz = /bits/ 64 <672000000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-787200000 {
|
|
opp-hz = /bits/ 64 <787200000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
|
|
};
|
|
|
|
opp-902400000 {
|
|
opp-hz = /bits/ 64 <902400000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1017600000 {
|
|
opp-hz = /bits/ 64 <1017600000>;
|
|
opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>;
|
|
};
|
|
|
|
opp-1132800000 {
|
|
opp-hz = /bits/ 64 <1132800000>;
|
|
opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1248000000 {
|
|
opp-hz = /bits/ 64 <1248000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>;
|
|
};
|
|
|
|
opp-1344000000 {
|
|
opp-hz = /bits/ 64 <1344000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1440000000 {
|
|
opp-hz = /bits/ 64 <1440000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1459200000 {
|
|
opp-hz = /bits/ 64 <1459200000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1536000000 {
|
|
opp-hz = /bits/ 64 <1536000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1574400000 {
|
|
opp-hz = /bits/ 64 <1574400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1651200000 {
|
|
opp-hz = /bits/ 64 <1651200000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1689600000 {
|
|
opp-hz = /bits/ 64 <1689600000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1747200000 {
|
|
opp-hz = /bits/ 64 <1747200000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1804800000 {
|
|
opp-hz = /bits/ 64 <1804800000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
|
|
};
|
|
|
|
opp-1843200000 {
|
|
opp-hz = /bits/ 64 <1843200000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
|
|
};
|
|
|
|
opp-1920000000 {
|
|
opp-hz = /bits/ 64 <1920000000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-1939200000 {
|
|
opp-hz = /bits/ 64 <1939200000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2035200000 {
|
|
opp-hz = /bits/ 64 <2035200000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2150400000 {
|
|
opp-hz = /bits/ 64 <2150400000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2265600000 {
|
|
opp-hz = /bits/ 64 <2265600000>;
|
|
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>;
|
|
};
|
|
};
|
|
|
|
cpu2_opp_table: opp-table-cpu2 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-460800000 {
|
|
opp-hz = /bits/ 64 <460800000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-499200000 {
|
|
opp-hz = /bits/ 64 <499200000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-576000000 {
|
|
opp-hz = /bits/ 64 <576000000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-614400000 {
|
|
opp-hz = /bits/ 64 <614400000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-691200000 {
|
|
opp-hz = /bits/ 64 <691200000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-729600000 {
|
|
opp-hz = /bits/ 64 <729600000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-806400000 {
|
|
opp-hz = /bits/ 64 <806400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-844800000 {
|
|
opp-hz = /bits/ 64 <844800000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-902400000 {
|
|
opp-hz = /bits/ 64 <902400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-960000000 {
|
|
opp-hz = /bits/ 64 <960000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1036800000 {
|
|
opp-hz = /bits/ 64 <1036800000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1075200000 {
|
|
opp-hz = /bits/ 64 <1075200000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1152000000 {
|
|
opp-hz = /bits/ 64 <1152000000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1190400000 {
|
|
opp-hz = /bits/ 64 <1190400000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1267200000 {
|
|
opp-hz = /bits/ 64 <1267200000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1286400000 {
|
|
opp-hz = /bits/ 64 <1286400000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1382400000 {
|
|
opp-hz = /bits/ 64 <1382400000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1401600000 {
|
|
opp-hz = /bits/ 64 <1401600000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1497600000 {
|
|
opp-hz = /bits/ 64 <1497600000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1612800000 {
|
|
opp-hz = /bits/ 64 <1612800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1708800000 {
|
|
opp-hz = /bits/ 64 <1708800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1728000000 {
|
|
opp-hz = /bits/ 64 <1728000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1824000000 {
|
|
opp-hz = /bits/ 64 <1824000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1843200000 {
|
|
opp-hz = /bits/ 64 <1843200000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1920000000 {
|
|
opp-hz = /bits/ 64 <1920000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1958400000 {
|
|
opp-hz = /bits/ 64 <1958400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2035200000 {
|
|
opp-hz = /bits/ 64 <2035200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2073600000 {
|
|
opp-hz = /bits/ 64 <2073600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2131200000 {
|
|
opp-hz = /bits/ 64 <2131200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2188800000 {
|
|
opp-hz = /bits/ 64 <2188800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2246400000 {
|
|
opp-hz = /bits/ 64 <2246400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2304000000 {
|
|
opp-hz = /bits/ 64 <2304000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2323200000 {
|
|
opp-hz = /bits/ 64 <2323200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2380800000 {
|
|
opp-hz = /bits/ 64 <2380800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2400000000 {
|
|
opp-hz = /bits/ 64 <2400000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2438400000 {
|
|
opp-hz = /bits/ 64 <2438400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2515200000 {
|
|
opp-hz = /bits/ 64 <2515200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2572800000 {
|
|
opp-hz = /bits/ 64 <2572800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2630400000 {
|
|
opp-hz = /bits/ 64 <2630400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2707200000 {
|
|
opp-hz = /bits/ 64 <2707200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2764800000 {
|
|
opp-hz = /bits/ 64 <2764800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2841600000 {
|
|
opp-hz = /bits/ 64 <2841600000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2899200000 {
|
|
opp-hz = /bits/ 64 <2899200000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2956800000 {
|
|
opp-hz = /bits/ 64 <2956800000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3014400000 {
|
|
opp-hz = /bits/ 64 <3014400000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3072000000 {
|
|
opp-hz = /bits/ 64 <3072000000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3148800000 {
|
|
opp-hz = /bits/ 64 <3148800000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
|
|
};
|
|
};
|
|
|
|
cpu5_opp_table: opp-table-cpu5 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-460800000 {
|
|
opp-hz = /bits/ 64 <460800000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-499200000 {
|
|
opp-hz = /bits/ 64 <499200000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-576000000 {
|
|
opp-hz = /bits/ 64 <576000000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-614400000 {
|
|
opp-hz = /bits/ 64 <614400000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-691200000 {
|
|
opp-hz = /bits/ 64 <691200000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-729600000 {
|
|
opp-hz = /bits/ 64 <729600000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-806400000 {
|
|
opp-hz = /bits/ 64 <806400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-844800000 {
|
|
opp-hz = /bits/ 64 <844800000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-902400000 {
|
|
opp-hz = /bits/ 64 <902400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-960000000 {
|
|
opp-hz = /bits/ 64 <960000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1036800000 {
|
|
opp-hz = /bits/ 64 <1036800000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1075200000 {
|
|
opp-hz = /bits/ 64 <1075200000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1152000000 {
|
|
opp-hz = /bits/ 64 <1152000000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1190400000 {
|
|
opp-hz = /bits/ 64 <1190400000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1267200000 {
|
|
opp-hz = /bits/ 64 <1267200000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1286400000 {
|
|
opp-hz = /bits/ 64 <1286400000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1382400000 {
|
|
opp-hz = /bits/ 64 <1382400000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1401600000 {
|
|
opp-hz = /bits/ 64 <1401600000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1497600000 {
|
|
opp-hz = /bits/ 64 <1497600000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1612800000 {
|
|
opp-hz = /bits/ 64 <1612800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1708800000 {
|
|
opp-hz = /bits/ 64 <1708800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1728000000 {
|
|
opp-hz = /bits/ 64 <1728000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1824000000 {
|
|
opp-hz = /bits/ 64 <1824000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1843200000 {
|
|
opp-hz = /bits/ 64 <1843200000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1920000000 {
|
|
opp-hz = /bits/ 64 <1920000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-1958400000 {
|
|
opp-hz = /bits/ 64 <1958400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2035200000 {
|
|
opp-hz = /bits/ 64 <2035200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2073600000 {
|
|
opp-hz = /bits/ 64 <2073600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2131200000 {
|
|
opp-hz = /bits/ 64 <2131200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2188800000 {
|
|
opp-hz = /bits/ 64 <2188800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2246400000 {
|
|
opp-hz = /bits/ 64 <2246400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2304000000 {
|
|
opp-hz = /bits/ 64 <2304000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2323200000 {
|
|
opp-hz = /bits/ 64 <2323200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2380800000 {
|
|
opp-hz = /bits/ 64 <2380800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2400000000 {
|
|
opp-hz = /bits/ 64 <2400000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2438400000 {
|
|
opp-hz = /bits/ 64 <2438400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2515200000 {
|
|
opp-hz = /bits/ 64 <2515200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2572800000 {
|
|
opp-hz = /bits/ 64 <2572800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2630400000 {
|
|
opp-hz = /bits/ 64 <2630400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2707200000 {
|
|
opp-hz = /bits/ 64 <2707200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2764800000 {
|
|
opp-hz = /bits/ 64 <2764800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2841600000 {
|
|
opp-hz = /bits/ 64 <2841600000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2899200000 {
|
|
opp-hz = /bits/ 64 <2899200000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2956800000 {
|
|
opp-hz = /bits/ 64 <2956800000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3014400000 {
|
|
opp-hz = /bits/ 64 <3014400000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3072000000 {
|
|
opp-hz = /bits/ 64 <3072000000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3148800000 {
|
|
opp-hz = /bits/ 64 <3148800000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
|
|
};
|
|
};
|
|
|
|
cpu7_opp_table: opp-table-cpu7 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-480000000 {
|
|
opp-hz = /bits/ 64 <480000000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-499200000 {
|
|
opp-hz = /bits/ 64 <499200000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-576000000 {
|
|
opp-hz = /bits/ 64 <576000000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
|
|
};
|
|
|
|
opp-614400000 {
|
|
opp-hz = /bits/ 64 <614400000>;
|
|
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-672000000 {
|
|
opp-hz = /bits/ 64 <672000000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-729600000 {
|
|
opp-hz = /bits/ 64 <729600000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-787200000 {
|
|
opp-hz = /bits/ 64 <787200000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-844800000 {
|
|
opp-hz = /bits/ 64 <844800000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-902400000 {
|
|
opp-hz = /bits/ 64 <902400000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-940800000 {
|
|
opp-hz = /bits/ 64 <940800000>;
|
|
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
|
|
};
|
|
|
|
opp-1017600000 {
|
|
opp-hz = /bits/ 64 <1017600000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1075200000 {
|
|
opp-hz = /bits/ 64 <1075200000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1132800000 {
|
|
opp-hz = /bits/ 64 <1132800000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
|
|
};
|
|
|
|
opp-1190400000 {
|
|
opp-hz = /bits/ 64 <1190400000>;
|
|
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1248000000 {
|
|
opp-hz = /bits/ 64 <1248000000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1305600000 {
|
|
opp-hz = /bits/ 64 <1305600000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1363200000 {
|
|
opp-hz = /bits/ 64 <1363200000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
|
|
};
|
|
|
|
opp-1420800000 {
|
|
opp-hz = /bits/ 64 <1420800000>;
|
|
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1478400000 {
|
|
opp-hz = /bits/ 64 <1478400000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1555200000 {
|
|
opp-hz = /bits/ 64 <1555200000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1593600000 {
|
|
opp-hz = /bits/ 64 <1593600000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1670400000 {
|
|
opp-hz = /bits/ 64 <1670400000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1708800000 {
|
|
opp-hz = /bits/ 64 <1708800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1804800000 {
|
|
opp-hz = /bits/ 64 <1804800000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1824000000 {
|
|
opp-hz = /bits/ 64 <1824000000>;
|
|
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
|
|
};
|
|
|
|
opp-1939200000 {
|
|
opp-hz = /bits/ 64 <1939200000>;
|
|
opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2035200000 {
|
|
opp-hz = /bits/ 64 <2035200000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2073600000 {
|
|
opp-hz = /bits/ 64 <2073600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2112000000 {
|
|
opp-hz = /bits/ 64 <2112000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2169600000 {
|
|
opp-hz = /bits/ 64 <2169600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2208000000 {
|
|
opp-hz = /bits/ 64 <2208000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2246400000 {
|
|
opp-hz = /bits/ 64 <2246400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2304000000 {
|
|
opp-hz = /bits/ 64 <2304000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2342400000 {
|
|
opp-hz = /bits/ 64 <2342400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2380800000 {
|
|
opp-hz = /bits/ 64 <2380800000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2438400000 {
|
|
opp-hz = /bits/ 64 <2438400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2457600000 {
|
|
opp-hz = /bits/ 64 <2457600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2496000000 {
|
|
opp-hz = /bits/ 64 <2496000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2553600000 {
|
|
opp-hz = /bits/ 64 <2553600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
|
|
};
|
|
|
|
opp-2630400000 {
|
|
opp-hz = /bits/ 64 <2630400000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2688000000 {
|
|
opp-hz = /bits/ 64 <2688000000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
|
|
};
|
|
|
|
opp-2745600000 {
|
|
opp-hz = /bits/ 64 <2745600000>;
|
|
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2803200000 {
|
|
opp-hz = /bits/ 64 <2803200000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2880000000 {
|
|
opp-hz = /bits/ 64 <2880000000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2937600000 {
|
|
opp-hz = /bits/ 64 <2937600000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-2995200000 {
|
|
opp-hz = /bits/ 64 <2995200000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3052800000 {
|
|
opp-hz = /bits/ 64 <3052800000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
|
|
};
|
|
|
|
opp-3187200000 {
|
|
opp-hz = /bits/ 64 <3187200000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
|
|
};
|
|
|
|
opp-3302400000 {
|
|
opp-hz = /bits/ 64 <3302400000>;
|
|
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
|
|
};
|
|
};
|
|
|
|
pmu-a520 {
|
|
compatible = "arm,cortex-a520-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
|
|
};
|
|
|
|
pmu-a720 {
|
|
compatible = "arm,cortex-a720-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
|
|
};
|
|
|
|
pmu-x4 {
|
|
compatible = "arm,cortex-x4-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
cpu_pd0: power-domain-cpu0 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&silver_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd1: power-domain-cpu1 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&silver_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd2: power-domain-cpu2 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd3: power-domain-cpu3 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd4: power-domain-cpu4 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd5: power-domain-cpu5 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd6: power-domain-cpu6 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_cpu_sleep_0>;
|
|
};
|
|
|
|
cpu_pd7: power-domain-cpu7 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&cluster_pd>;
|
|
domain-idle-states = <&gold_plus_cpu_sleep_0>;
|
|
};
|
|
|
|
cluster_pd: power-domain-cluster {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&cluster_sleep_0>,
|
|
<&cluster_sleep_1>;
|
|
};
|
|
};
|
|
|
|
reserved_memory: reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
hyp_mem: hyp@80000000 {
|
|
reg = <0 0x80000000 0 0xe00000>;
|
|
no-map;
|
|
};
|
|
|
|
cpusys_vm_mem: cpusys-vm@80e00000 {
|
|
reg = <0 0x80e00000 0 0x400000>;
|
|
no-map;
|
|
};
|
|
|
|
/* Merged xbl_dtlog, xbl_ramdump and aop_image regions */
|
|
xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
|
|
reg = <0 0x81a00000 0 0x260000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_cmd_db_mem: aop-cmd-db@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
reg = <0 0x81c60000 0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
/* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */
|
|
aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
|
|
reg = <0 0x81c80000 0 0x75000>;
|
|
no-map;
|
|
};
|
|
|
|
/* Secdata region can be reused by apps */
|
|
|
|
smem: smem@81d00000 {
|
|
compatible = "qcom,smem";
|
|
reg = <0 0x81d00000 0 0x200000>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
no-map;
|
|
};
|
|
|
|
adsp_mhi_mem: adsp-mhi@81f00000 {
|
|
reg = <0 0x81f00000 0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
pvmfw_mem: pvmfw@824a0000 {
|
|
reg = <0 0x824a0000 0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
global_sync_mem: global-sync@82600000 {
|
|
reg = <0 0x82600000 0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
tz_stat_mem: tz-stat@82700000 {
|
|
reg = <0 0x82700000 0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
qdss_mem: qdss@82800000 {
|
|
reg = <0 0x82800000 0 0x2000000>;
|
|
no-map;
|
|
};
|
|
|
|
qlink_logging_mem: qlink-logging@84800000 {
|
|
reg = <0 0x84800000 0 0x200000>;
|
|
no-map;
|
|
};
|
|
|
|
mpss_dsm_mem: mpss-dsm@86b00000 {
|
|
reg = <0 0x86b00000 0 0x4900000>;
|
|
no-map;
|
|
};
|
|
|
|
mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
|
|
reg = <0 0x8b400000 0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
mpss_mem: mpss@8bc00000 {
|
|
reg = <0 0x8bc00000 0 0xf400000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
|
|
reg = <0 0x9b000000 0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
ipa_fw_mem: ipa-fw@9b080000 {
|
|
reg = <0 0x9b080000 0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
ipa_gsi_mem: ipa-gsi@9b090000 {
|
|
reg = <0 0x9b090000 0 0xa000>;
|
|
no-map;
|
|
};
|
|
|
|
gpu_micro_code_mem: gpu-micro-code@9b09a000 {
|
|
reg = <0 0x9b09a000 0 0x2000>;
|
|
no-map;
|
|
};
|
|
|
|
spss_region_mem: spss@9b0a0000 {
|
|
reg = <0 0x9b0a0000 0 0x1e0000>;
|
|
no-map;
|
|
};
|
|
|
|
/* First part of the "SPU secure shared memory" region */
|
|
spu_tz_shared_mem: spu-tz-shared@9b280000 {
|
|
reg = <0 0x9b280000 0 0x60000>;
|
|
no-map;
|
|
};
|
|
|
|
/* Second part of the "SPU secure shared memory" region */
|
|
spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
|
|
reg = <0 0x9b2e0000 0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
camera_mem: camera@9b300000 {
|
|
reg = <0 0x9b300000 0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
video_mem: video@9bb00000 {
|
|
reg = <0 0x9bb00000 0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
cvp_mem: cvp@9c300000 {
|
|
reg = <0 0x9c300000 0 0x700000>;
|
|
no-map;
|
|
};
|
|
|
|
cdsp_mem: cdsp@9ca00000 {
|
|
reg = <0 0x9ca00000 0 0x1400000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
|
|
reg = <0 0x9de00000 0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
|
|
reg = <0 0x9de80000 0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
adspslpi_mem: adspslpi@9df00000 {
|
|
reg = <0 0x9df00000 0 0x4080000>;
|
|
no-map;
|
|
};
|
|
|
|
rmtfs_mem: rmtfs@d7c00000 {
|
|
compatible = "qcom,rmtfs-mem";
|
|
reg = <0 0xd7c00000 0 0x400000>;
|
|
no-map;
|
|
|
|
qcom,client-id = <1>;
|
|
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
|
|
};
|
|
|
|
/* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
|
|
tz_merged_mem: tz-merged@d8000000 {
|
|
reg = <0 0xd8000000 0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
hwfence_shbuf: hwfence-shbuf@e6440000 {
|
|
reg = <0 0xe6440000 0 0x2dd000>;
|
|
no-map;
|
|
};
|
|
|
|
trust_ui_vm_mem: trust-ui-vm@f3800000 {
|
|
reg = <0 0xf3800000 0 0x4400000>;
|
|
no-map;
|
|
};
|
|
|
|
oem_vm_mem: oem-vm@f7c00000 {
|
|
reg = <0 0xf7c00000 0 0x4c00000>;
|
|
no-map;
|
|
};
|
|
|
|
llcc_lpi_mem: llcc-lpi@ff800000 {
|
|
reg = <0 0xff800000 0 0x600000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,smem = <443>, <429>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
smp2p_adsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_adsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,smem = <94>, <432>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
smp2p_cdsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_cdsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,smem = <435>, <428>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
smp2p_modem_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_modem_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
ipa_smp2p_out: ipa-ap-to-modem {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
ipa_smp2p_in: ipa-modem-to-ap {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc@0 {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0 0 0 0 0x10 0>;
|
|
ranges = <0 0 0 0 0x10 0>;
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,sm8650-gcc";
|
|
reg = <0 0x00100000 0 0x1f4200>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&bi_tcxo_ao_div2>,
|
|
<&sleep_clk>,
|
|
<&pcie0_phy>,
|
|
<&pcie1_phy QMP_PCIE_PIPE_CLK>,
|
|
<&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
|
|
<&ufs_mem_phy 0>,
|
|
<&ufs_mem_phy 1>,
|
|
<&ufs_mem_phy 2>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
ipcc: mailbox@406000 {
|
|
compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
|
|
reg = <0 0x00406000 0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
gpi_dma2: dma-controller@800000 {
|
|
compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x00800000 0 0x60000>;
|
|
|
|
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0x3f>;
|
|
#dma-cells = <3>;
|
|
|
|
iommus = <&apps_smmu 0x436 0>;
|
|
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_1: geniqup@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0 0x008c0000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
clock-names = "m-ahb",
|
|
"s-ahb";
|
|
|
|
iommus = <&apps_smmu 0x423 0>;
|
|
|
|
dma-coherent;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@880000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00880000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c8_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@880000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00880000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@884000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00884000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c9_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@884000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00884000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00888000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c10_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@888000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00888000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x0088c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c11_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi11: spi@88c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x0088c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@890000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00890000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c12_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi12: spi@890000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00890000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c@894000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00894000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c13_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi13: spi@894000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00894000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart14: serial@898000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0 0x00898000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_128mhz>;
|
|
|
|
pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart15: serial@89c000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0 0x0089c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
pinctrl-0 = <&qup_uart15_default>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c_master_hub_0: geniqup@9c0000 {
|
|
compatible = "qcom,geni-se-i2c-master-hub";
|
|
reg = <0 0x009c0000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
|
|
clock-names = "s-ahb";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
i2c_hub_0: i2c@980000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00980000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c0_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_1: i2c@984000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00984000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c1_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_2: i2c@988000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00988000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c2_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_3: i2c@98c000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x0098c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c3_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_4: i2c@990000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00990000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c4_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_5: i2c@994000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00994000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c5_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_6: i2c@998000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x00998000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c6_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_7: i2c@99c000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x0099c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c7_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_8: i2c@9a0000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x009a0000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c8_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_hub_9: i2c@9a4000 {
|
|
compatible = "qcom,geni-i2c-master-hub";
|
|
reg = <0 0x009a4000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
|
|
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
|
|
clock-names = "se",
|
|
"core";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
pinctrl-0 = <&hub_i2c9_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma1: dma-controller@a00000 {
|
|
compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x00a00000 0 0x60000>;
|
|
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xc>;
|
|
#dma-cells = <3>;
|
|
|
|
iommus = <&apps_smmu 0xb6 0>;
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_0: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0 0x00ac0000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
clock-names = "m-ahb",
|
|
"s-ahb";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core";
|
|
|
|
iommus = <&apps_smmu 0xa3 0>;
|
|
|
|
dma-coherent;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a80000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c0_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a80000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a84000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c1_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a84000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a88000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_240mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c2_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a88000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_240mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a8c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c3_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@a8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a8c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a90000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c4_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@a90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a90000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@a94000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a94000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c5_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@a94000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a94000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@a98000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a98000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c6_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi6: spi@a98000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a98000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@a9c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a9c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c7_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@a9c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a9c000 0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
|
|
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cnoc_main: interconnect@1500000 {
|
|
compatible = "qcom,sm8650-cnoc-main";
|
|
reg = <0 0x01500000 0 0x14080>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
config_noc: interconnect@1600000 {
|
|
compatible = "qcom,sm8650-config-noc";
|
|
reg = <0 0x01600000 0 0x6200>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,sm8650-system-noc";
|
|
reg = <0 0x01680000 0 0x1d080>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
pcie_noc: interconnect@16c0000 {
|
|
compatible = "qcom,sm8650-pcie-anoc";
|
|
reg = <0 0x016c0000 0 0x12200>;
|
|
|
|
clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,sm8650-aggre1-noc";
|
|
reg = <0 0x016e0000 0 0x16400>;
|
|
|
|
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,sm8650-aggre2-noc";
|
|
reg = <0 0x01700000 0 0x1e400>;
|
|
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1780000 {
|
|
compatible = "qcom,sm8650-mmss-noc";
|
|
reg = <0 0x01780000 0 0x5b800>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
rng: rng@10c3000 {
|
|
compatible = "qcom,sm8650-trng", "qcom,trng";
|
|
reg = <0 0x010c3000 0 0x1000>;
|
|
};
|
|
|
|
pcie0: pcie@1c00000 {
|
|
device_type = "pci";
|
|
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
|
|
reg = <0 0x01c00000 0 0x3000>,
|
|
<0 0x60000000 0 0xf1d>,
|
|
<0 0x60000f20 0 0xa8>,
|
|
<0 0x60001000 0 0x1000>,
|
|
<0 0x60100000 0 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a",
|
|
"ddrss_sf_tbu",
|
|
"noc_aggr",
|
|
"cnoc_sf_axi";
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>;
|
|
reset-names = "pci";
|
|
|
|
interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "pcie-mem",
|
|
"cpu-pcie";
|
|
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
|
|
operating-points-v2 = <&pcie0_opp_table>;
|
|
|
|
iommu-map = <0 &apps_smmu 0x1400 0x1>,
|
|
<0x100 &apps_smmu 0x1401 0x1>;
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
#interrupt-cells = <1>;
|
|
|
|
msi-map = <0x0 &gic_its 0x1400 0x1>,
|
|
<0x100 &gic_its 0x1401 0x1>;
|
|
msi-map-mask = <0xff00>;
|
|
|
|
linux,pci-domain = <0>;
|
|
num-lanes = <2>;
|
|
bus-range = <0 0xff>;
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
|
|
<0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
|
|
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
|
|
pcie0_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
/* GEN 1 x1 */
|
|
opp-2500000 {
|
|
opp-hz = /bits/ 64 <2500000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <250000 1>;
|
|
};
|
|
|
|
/* GEN 1 x2 and GEN 2 x1 */
|
|
opp-5000000 {
|
|
opp-hz = /bits/ 64 <5000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <500000 1>;
|
|
};
|
|
|
|
/* GEN 2 x2 */
|
|
opp-10000000 {
|
|
opp-hz = /bits/ 64 <10000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <1000000 1>;
|
|
};
|
|
|
|
/* GEN 3 x1 */
|
|
opp-8000000 {
|
|
opp-hz = /bits/ 64 <8000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
opp-peak-kBps = <984500 1>;
|
|
};
|
|
|
|
/* GEN 3 x2 */
|
|
opp-16000000 {
|
|
opp-hz = /bits/ 64 <16000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
opp-peak-kBps = <1969000 1>;
|
|
};
|
|
};
|
|
|
|
pcieport0: pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie0_phy: phy@1c06000 {
|
|
compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
|
|
reg = <0 0x01c06000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&tcsr TCSR_PCIE_0_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"cfg_ahb",
|
|
"ref",
|
|
"rchng",
|
|
"pipe";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
power-domains = <&gcc PCIE_0_PHY_GDSC>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie0_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@1c08000 {
|
|
device_type = "pci";
|
|
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
|
|
reg = <0 0x01c08000 0 0x3000>,
|
|
<0 0x40000000 0 0xf1d>,
|
|
<0 0x40000f20 0 0xa8>,
|
|
<0 0x40001000 0 0x1000>,
|
|
<0 0x40100000 0 0x100000>;
|
|
reg-names = "parf",
|
|
"dbi",
|
|
"elbi",
|
|
"atu",
|
|
"config";
|
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "msi0",
|
|
"msi1",
|
|
"msi2",
|
|
"msi3",
|
|
"msi4",
|
|
"msi5",
|
|
"msi6",
|
|
"msi7",
|
|
"global";
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a",
|
|
"ddrss_sf_tbu",
|
|
"noc_aggr",
|
|
"cnoc_sf_axi";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>,
|
|
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
|
|
reset-names = "pci",
|
|
"link_down";
|
|
|
|
interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "pcie-mem",
|
|
"cpu-pcie";
|
|
|
|
power-domains = <&gcc PCIE_1_GDSC>;
|
|
|
|
operating-points-v2 = <&pcie1_opp_table>;
|
|
|
|
iommu-map = <0 &apps_smmu 0x1480 0x1>,
|
|
<0x100 &apps_smmu 0x1481 0x1>;
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
#interrupt-cells = <1>;
|
|
|
|
msi-map = <0x0 &gic_its 0x1480 0x1>,
|
|
<0x100 &gic_its 0x1481 0x1>;
|
|
msi-map-mask = <0xff00>;
|
|
|
|
linux,pci-domain = <1>;
|
|
num-lanes = <2>;
|
|
bus-range = <0 0xff>;
|
|
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
dma-coherent;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
|
|
<0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
|
|
|
|
status = "disabled";
|
|
|
|
pcie1_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
/* GEN 1 x1 */
|
|
opp-2500000 {
|
|
opp-hz = /bits/ 64 <2500000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <250000 1>;
|
|
};
|
|
|
|
/* GEN 1 x2 and GEN 2 x1 */
|
|
opp-5000000 {
|
|
opp-hz = /bits/ 64 <5000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <500000 1>;
|
|
};
|
|
|
|
/* GEN 2 x2 */
|
|
opp-10000000 {
|
|
opp-hz = /bits/ 64 <10000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
opp-peak-kBps = <1000000 1>;
|
|
};
|
|
|
|
/* GEN 3 x1 */
|
|
opp-8000000 {
|
|
opp-hz = /bits/ 64 <8000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
opp-peak-kBps = <984500 1>;
|
|
};
|
|
|
|
/* GEN 3 x2 and GEN 4 x1 */
|
|
opp-16000000 {
|
|
opp-hz = /bits/ 64 <16000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
opp-peak-kBps = <1969000 1>;
|
|
};
|
|
|
|
/* GEN 4 x2 */
|
|
opp-32000000 {
|
|
opp-hz = /bits/ 64 <32000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
opp-peak-kBps = <3938000 1>;
|
|
};
|
|
};
|
|
|
|
pcie@0 {
|
|
device_type = "pci";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie1_phy: phy@1c0e000 {
|
|
compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
|
|
reg = <0 0x01c0e000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&tcsr TCSR_PCIE_1_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"cfg_ahb",
|
|
"ref",
|
|
"rchng",
|
|
"pipe";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>,
|
|
<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
|
|
reset-names = "phy",
|
|
"phy_nocsr";
|
|
|
|
power-domains = <&gcc PCIE_1_PHY_GDSC>;
|
|
|
|
#clock-cells = <1>;
|
|
clock-output-names = "pcie1_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
cryptobam: dma-controller@1dc4000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0 0x01dc4000 0 0x28000>;
|
|
|
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
#dma-cells = <1>;
|
|
|
|
iommus = <&apps_smmu 0x480 0>,
|
|
<&apps_smmu 0x481 0>;
|
|
|
|
qcom,ee = <0>;
|
|
qcom,num-ees = <4>;
|
|
num-channels = <20>;
|
|
qcom,controlled-remotely;
|
|
};
|
|
|
|
crypto: crypto@1dfa000 {
|
|
compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
|
|
reg = <0 0x01dfa000 0 0x6000>;
|
|
|
|
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "memory";
|
|
|
|
dmas = <&cryptobam 4>, <&cryptobam 5>;
|
|
dma-names = "rx", "tx";
|
|
|
|
iommus = <&apps_smmu 0x480 0>,
|
|
<&apps_smmu 0x481 0>;
|
|
};
|
|
|
|
ufs_mem_phy: phy@1d80000 {
|
|
compatible = "qcom,sm8650-qmp-ufs-phy";
|
|
reg = <0 0x01d80000 0 0x2000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&tcsr TCSR_UFS_CLKREF_EN>;
|
|
clock-names = "ref",
|
|
"ref_aux",
|
|
"qref";
|
|
|
|
resets = <&ufs_mem_hc 0>;
|
|
reset-names = "ufsphy";
|
|
|
|
power-domains = <&gcc UFS_MEM_PHY_GDSC>;
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_hc: ufshc@1d84000 {
|
|
compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
|
reg = <0 0x01d84000 0 0x3000>;
|
|
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&tcsr TCSR_UFS_PAD_CLKREF_EN>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
clock-names = "core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
|
|
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "ufs-ddr",
|
|
"cpu-ufs";
|
|
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
operating-points-v2 = <&ufs_opp_table>;
|
|
|
|
iommus = <&apps_smmu 0x60 0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
qcom,ice = <&ice>;
|
|
|
|
phys = <&ufs_mem_phy>;
|
|
phy-names = "ufsphy";
|
|
|
|
#reset-cells = <1>;
|
|
|
|
status = "disabled";
|
|
|
|
ufs_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <100000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-201500000 {
|
|
opp-hz = /bits/ 64 <201500000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <201500000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-403000000 {
|
|
opp-hz = /bits/ 64 <403000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <403000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ice: crypto@1d88000 {
|
|
compatible = "qcom,sm8650-inline-crypto-engine",
|
|
"qcom,inline-crypto-engine";
|
|
reg = <0 0x01d88000 0 0x18000>;
|
|
|
|
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0 0x01f40000 0 0x20000>;
|
|
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: clock-controller@1fc0000 {
|
|
compatible = "qcom,sm8650-tcsr", "syscon";
|
|
reg = <0 0x01fc0000 0 0xa0000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpu: gpu@3d00000 {
|
|
compatible = "qcom,adreno-43051401", "qcom,adreno";
|
|
reg = <0x0 0x03d00000 0x0 0x40000>,
|
|
<0x0 0x03d9e000 0x0 0x2000>,
|
|
<0x0 0x03d61000 0x0 0x800>;
|
|
reg-names = "kgsl_3d0_reg_memory",
|
|
"cx_mem",
|
|
"cx_dbgc";
|
|
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
iommus = <&adreno_smmu 0 0x0>,
|
|
<&adreno_smmu 1 0x0>;
|
|
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
|
|
qcom,gmu = <&gmu>;
|
|
#cooling-cells = <2>;
|
|
|
|
interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "gfx-mem";
|
|
|
|
status = "disabled";
|
|
|
|
zap-shader {
|
|
memory-region = <&gpu_micro_code_mem>;
|
|
};
|
|
|
|
/* Speedbin needs more work on A740+, keep only lower freqs */
|
|
gpu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-231000000 {
|
|
opp-hz = /bits/ 64 <231000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
|
opp-peak-kBps = <2136718>;
|
|
};
|
|
|
|
opp-310000000 {
|
|
opp-hz = /bits/ 64 <310000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
|
opp-peak-kBps = <2136718>;
|
|
};
|
|
|
|
opp-366000000 {
|
|
opp-hz = /bits/ 64 <366000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
|
opp-peak-kBps = <6074218>;
|
|
};
|
|
|
|
opp-422000000 {
|
|
opp-hz = /bits/ 64 <422000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
opp-peak-kBps = <8171875>;
|
|
};
|
|
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
|
opp-peak-kBps = <8171875>;
|
|
};
|
|
|
|
opp-578000000 {
|
|
opp-hz = /bits/ 64 <578000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
opp-peak-kBps = <8171875>;
|
|
};
|
|
|
|
opp-629000000 {
|
|
opp-hz = /bits/ 64 <629000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
|
opp-peak-kBps = <10687500>;
|
|
};
|
|
|
|
opp-680000000 {
|
|
opp-hz = /bits/ 64 <680000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
opp-peak-kBps = <12449218>;
|
|
};
|
|
|
|
opp-720000000 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
opp-peak-kBps = <12449218>;
|
|
};
|
|
|
|
opp-770000000 {
|
|
opp-hz = /bits/ 64 <770000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
opp-peak-kBps = <12449218>;
|
|
};
|
|
|
|
opp-834000000 {
|
|
opp-hz = /bits/ 64 <834000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
opp-peak-kBps = <14398437>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gmu: gmu@3d6a000 {
|
|
compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
|
|
reg = <0x0 0x03d6a000 0x0 0x35000>,
|
|
<0x0 0x03d50000 0x0 0x10000>,
|
|
<0x0 0x0b280000 0x0 0x10000>;
|
|
reg-names = "gmu", "rscc", "gmu_pdc";
|
|
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "hfi", "gmu";
|
|
|
|
clocks = <&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_DEMET_CLK>;
|
|
clock-names = "ahb",
|
|
"gmu",
|
|
"cxo",
|
|
"axi",
|
|
"memnoc",
|
|
"hub",
|
|
"demet";
|
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>,
|
|
<&gpucc GPU_GX_GDSC>;
|
|
power-domain-names = "cx",
|
|
"gx";
|
|
|
|
iommus = <&adreno_smmu 5 0x0>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
operating-points-v2 = <&gmu_opp_table>;
|
|
|
|
gmu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-260000000 {
|
|
opp-hz = /bits/ 64 <260000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
opp-625000000 {
|
|
opp-hz = /bits/ 64 <625000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sm8650-gpucc";
|
|
reg = <0 0x03d90000 0 0xa000>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
adreno_smmu: iommu@3da0000 {
|
|
compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
|
|
"qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x03da0000 0x0 0x40000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <1>;
|
|
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>;
|
|
clock-names = "hlos",
|
|
"bus",
|
|
"iface",
|
|
"ahb";
|
|
power-domains = <&gpucc GPU_CX_GDSC>;
|
|
dma-coherent;
|
|
};
|
|
|
|
ipa: ipa@3f40000 {
|
|
compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
|
|
|
|
iommus = <&apps_smmu 0x4a0 0x0>,
|
|
<&apps_smmu 0x4a2 0x0>;
|
|
reg = <0 0x3f40000 0 0x10000>,
|
|
<0 0x3f50000 0 0x5000>,
|
|
<0 0x3e04000 0 0xfc000>;
|
|
reg-names = "ipa-reg",
|
|
"ipa-shared",
|
|
"gsi";
|
|
|
|
interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
|
|
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "ipa",
|
|
"gsi",
|
|
"ipa-clock-query",
|
|
"ipa-setup-ready";
|
|
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
clock-names = "core";
|
|
|
|
interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "memory",
|
|
"config";
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&ipa_smp2p_out 0>,
|
|
<&ipa_smp2p_out 1>;
|
|
qcom,smem-state-names = "ipa-clock-enabled-valid",
|
|
"ipa-clock-enabled";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
remoteproc_mpss: remoteproc@4080000 {
|
|
compatible = "qcom,sm8650-mpss-pas";
|
|
reg = <0x0 0x04080000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
|
|
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"ready",
|
|
"handover",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MSS>;
|
|
power-domain-names = "cx",
|
|
"mss";
|
|
|
|
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
|
|
<&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
|
|
<&qlink_logging_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_modem_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
qcom,remote-pid = <1>;
|
|
|
|
label = "mpss";
|
|
};
|
|
};
|
|
|
|
remoteproc_adsp: remoteproc@6800000 {
|
|
compatible = "qcom,sm8650-adsp-pas";
|
|
reg = <0x0 0x06800000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"ready",
|
|
"handover",
|
|
"stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_LCX>,
|
|
<&rpmhpd RPMHPD_LMX>;
|
|
power-domain-names = "lcx",
|
|
"lmx";
|
|
|
|
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_adsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
remoteproc_adsp_glink: glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
qcom,remote-pid = <2>;
|
|
|
|
label = "lpass";
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
|
|
label = "adsp";
|
|
|
|
qcom,non-secure-domain;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
|
|
iommus = <&apps_smmu 0x1003 0x80>,
|
|
<&apps_smmu 0x1043 0x20>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
|
|
iommus = <&apps_smmu 0x1004 0x80>,
|
|
<&apps_smmu 0x1044 0x20>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
|
|
iommus = <&apps_smmu 0x1005 0x80>,
|
|
<&apps_smmu 0x1045 0x20>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@6 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <6>;
|
|
|
|
iommus = <&apps_smmu 0x1006 0x80>,
|
|
<&apps_smmu 0x1046 0x20>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@7 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <7>;
|
|
|
|
iommus = <&apps_smmu 0x1007 0x40>,
|
|
<&apps_smmu 0x1067 0x0>,
|
|
<&apps_smmu 0x1087 0x0>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
gpr {
|
|
compatible = "qcom,gpr";
|
|
qcom,glink-channels = "adsp_apps";
|
|
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
|
|
qcom,intents = <512 20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
q6apm: service@1 {
|
|
compatible = "qcom,q6apm";
|
|
reg = <GPR_APM_MODULE_IID>;
|
|
#sound-dai-cells = <0>;
|
|
qcom,protection-domain = "avs/audio",
|
|
"msm/adsp/audio_pd";
|
|
|
|
q6apmbedai: bedais {
|
|
compatible = "qcom,q6apm-lpass-dais";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
q6apmdai: dais {
|
|
compatible = "qcom,q6apm-dais";
|
|
iommus = <&apps_smmu 0x1001 0x80>,
|
|
<&apps_smmu 0x1061 0x0>;
|
|
};
|
|
};
|
|
|
|
q6prm: service@2 {
|
|
compatible = "qcom,q6prm";
|
|
reg = <GPR_PRM_MODULE_IID>;
|
|
qcom,protection-domain = "avs/audio",
|
|
"msm/adsp/audio_pd";
|
|
|
|
q6prmcc: clock-controller {
|
|
compatible = "qcom,q6prm-lpass-clocks";
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lpass_wsa2macro: codec@6aa0000 {
|
|
compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
|
|
reg = <0 0x06aa0000 0 0x1000>;
|
|
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&lpass_vamacro>;
|
|
clock-names = "mclk",
|
|
"macro",
|
|
"dcodec",
|
|
"fsgen";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "wsa2-mclk";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
swr3: soundwire@6ab0000 {
|
|
compatible = "qcom,soundwire-v2.0.0";
|
|
reg = <0 0x06ab0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&lpass_wsa2macro>;
|
|
clock-names = "iface";
|
|
label = "WSA2";
|
|
|
|
pinctrl-0 = <&wsa2_swr_active>;
|
|
pinctrl-names = "default";
|
|
|
|
qcom,din-ports = <4>;
|
|
qcom,dout-ports = <9>;
|
|
|
|
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
|
|
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
|
|
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
|
|
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
|
|
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
|
|
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
|
|
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpass_rxmacro: codec@6ac0000 {
|
|
compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
|
|
reg = <0 0x06ac0000 0 0x1000>;
|
|
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&lpass_vamacro>;
|
|
clock-names = "mclk",
|
|
"macro",
|
|
"dcodec",
|
|
"fsgen";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mclk";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
swr1: soundwire@6ad0000 {
|
|
compatible = "qcom,soundwire-v2.0.0";
|
|
reg = <0 0x06ad0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&lpass_rxmacro>;
|
|
clock-names = "iface";
|
|
label = "RX";
|
|
|
|
pinctrl-0 = <&rx_swr_active>;
|
|
pinctrl-names = "default";
|
|
|
|
qcom,din-ports = <0>;
|
|
qcom,dout-ports = <11>;
|
|
|
|
qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
|
|
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
|
|
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
|
|
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
|
|
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
|
|
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
|
|
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
|
|
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
|
|
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpass_txmacro: codec@6ae0000 {
|
|
compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
|
|
reg = <0 0x06ae0000 0 0x1000>;
|
|
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&lpass_vamacro>;
|
|
clock-names = "mclk",
|
|
"macro",
|
|
"dcodec",
|
|
"fsgen";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mclk";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
lpass_wsamacro: codec@6b00000 {
|
|
compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
|
|
reg = <0 0x06b00000 0 0x1000>;
|
|
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&lpass_vamacro>;
|
|
clock-names = "mclk",
|
|
"macro",
|
|
"dcodec",
|
|
"fsgen";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mclk";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
swr0: soundwire@6b10000 {
|
|
compatible = "qcom,soundwire-v2.0.0";
|
|
reg = <0 0x06b10000 0 0x10000>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&lpass_wsamacro>;
|
|
clock-names = "iface";
|
|
label = "WSA";
|
|
|
|
pinctrl-0 = <&wsa_swr_active>;
|
|
pinctrl-names = "default";
|
|
|
|
qcom,din-ports = <4>;
|
|
qcom,dout-ports = <9>;
|
|
|
|
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
|
|
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
|
|
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
|
|
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
|
|
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
|
|
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
|
|
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
swr2: soundwire@6d30000 {
|
|
compatible = "qcom,soundwire-v2.0.0";
|
|
reg = <0 0x06d30000 0 0x10000>;
|
|
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "core", "wakeup";
|
|
clocks = <&lpass_txmacro>;
|
|
clock-names = "iface";
|
|
label = "TX";
|
|
|
|
pinctrl-0 = <&tx_swr_active>;
|
|
pinctrl-names = "default";
|
|
|
|
qcom,din-ports = <4>;
|
|
qcom,dout-ports = <0>;
|
|
|
|
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
|
|
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
|
|
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
|
|
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
|
|
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
|
|
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
|
|
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
|
|
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
|
|
qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpass_vamacro: codec@6d44000 {
|
|
compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
|
|
reg = <0 0x06d44000 0 0x1000>;
|
|
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
|
clock-names = "mclk",
|
|
"macro",
|
|
"dcodec";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "fsgen";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
lpass_tlmm: pinctrl@6e80000 {
|
|
compatible = "qcom,sm8650-lpass-lpi-pinctrl";
|
|
reg = <0 0x06e80000 0 0x20000>;
|
|
|
|
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
|
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
|
clock-names = "core", "audio";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&lpass_tlmm 0 0 23>;
|
|
|
|
tx_swr_active: tx-swr-active-state {
|
|
clk-pins {
|
|
pins = "gpio0";
|
|
function = "swr_tx_clk";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-disable;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio1", "gpio2", "gpio14";
|
|
function = "swr_tx_data";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
rx_swr_active: rx-swr-active-state {
|
|
clk-pins {
|
|
pins = "gpio3";
|
|
function = "swr_rx_clk";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-disable;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio4", "gpio5";
|
|
function = "swr_rx_data";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
dmic01_default: dmic01-default-state {
|
|
clk-pins {
|
|
pins = "gpio6";
|
|
function = "dmic1_clk";
|
|
drive-strength = <8>;
|
|
output-high;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio7";
|
|
function = "dmic1_data";
|
|
drive-strength = <8>;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
dmic23_default: dmic23-default-state {
|
|
clk-pins {
|
|
pins = "gpio8";
|
|
function = "dmic2_clk";
|
|
drive-strength = <8>;
|
|
output-high;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio9";
|
|
function = "dmic2_data";
|
|
drive-strength = <8>;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
wsa_swr_active: wsa-swr-active-state {
|
|
clk-pins {
|
|
pins = "gpio10";
|
|
function = "wsa_swr_clk";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-disable;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio11";
|
|
function = "wsa_swr_data";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
wsa2_swr_active: wsa2-swr-active-state {
|
|
clk-pins {
|
|
pins = "gpio15";
|
|
function = "wsa2_swr_clk";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-disable;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio16";
|
|
function = "wsa2_swr_data";
|
|
drive-strength = <2>;
|
|
slew-rate = <1>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
};
|
|
|
|
lpass_lpiaon_noc: interconnect@7400000 {
|
|
compatible = "qcom,sm8650-lpass-lpiaon-noc";
|
|
reg = <0 0x07400000 0 0x19080>;
|
|
|
|
#interconnect-cells = <2>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_lpicx_noc: interconnect@7430000 {
|
|
compatible = "qcom,sm8650-lpass-lpicx-noc";
|
|
reg = <0 0x07430000 0 0x3a200>;
|
|
|
|
#interconnect-cells = <2>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@7e40000 {
|
|
compatible = "qcom,sm8650-lpass-ag-noc";
|
|
reg = <0 0x07e40000 0 0xe080>;
|
|
|
|
#interconnect-cells = <2>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
sdhc_2: mmc@8804000 {
|
|
compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
|
|
reg = <0 0x08804000 0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "hc_irq",
|
|
"pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface",
|
|
"core",
|
|
"xo";
|
|
|
|
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "sdhc-ddr",
|
|
"cpu-sdhc";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
|
|
iommus = <&apps_smmu 0x540 0>;
|
|
|
|
bus-width = <4>;
|
|
|
|
/* Forbid SDR104/SDR50 - broken hw! */
|
|
sdhci-caps-mask = <0x3 0>;
|
|
|
|
qcom,dll-config = <0x0007642c>;
|
|
qcom,ddr-config = <0x80040868>;
|
|
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
|
|
sdhc2_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-19200000 {
|
|
opp-hz = /bits/ 64 <19200000>;
|
|
required-opps = <&rpmhpd_opp_min_svs>;
|
|
};
|
|
|
|
opp-50000000 {
|
|
opp-hz = /bits/ 64 <50000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
iris: video-codec@aa00000 {
|
|
compatible = "qcom,sm8650-iris";
|
|
reg = <0 0x0aa00000 0 0xf0000>;
|
|
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
|
|
<&videocc VIDEO_CC_MVS0_GDSC>,
|
|
<&rpmhpd RPMHPD_MXC>,
|
|
<&rpmhpd RPMHPD_MMCX>;
|
|
power-domain-names = "venus",
|
|
"vcodec0",
|
|
"mxc",
|
|
"mmcx";
|
|
|
|
operating-points-v2 = <&iris_opp_table>;
|
|
|
|
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
|
|
<&videocc VIDEO_CC_MVS0C_CLK>,
|
|
<&videocc VIDEO_CC_MVS0_CLK>;
|
|
clock-names = "iface",
|
|
"core",
|
|
"vcodec0_core";
|
|
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "cpu-cfg",
|
|
"video-mem";
|
|
|
|
memory-region = <&video_mem>;
|
|
|
|
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
|
|
<&videocc VIDEO_CC_XO_CLK_ARES>,
|
|
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
|
|
reset-names = "bus",
|
|
"xo",
|
|
"core";
|
|
|
|
iommus = <&apps_smmu 0x1940 0>,
|
|
<&apps_smmu 0x1947 0>;
|
|
|
|
dma-coherent;
|
|
|
|
/*
|
|
* IRIS firmware is signed by vendors, only
|
|
* enable in boards where the proper signed firmware
|
|
* is available.
|
|
*/
|
|
status = "disabled";
|
|
|
|
iris_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-196000000 {
|
|
opp-hz = /bits/ 64 <196000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs_d1>,
|
|
<&rpmhpd_opp_low_svs_d1>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>,
|
|
<&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-380000000 {
|
|
opp-hz = /bits/ 64 <380000000>;
|
|
required-opps = <&rpmhpd_opp_svs>,
|
|
<&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-435000000 {
|
|
opp-hz = /bits/ 64 <435000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>,
|
|
<&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-480000000 {
|
|
opp-hz = /bits/ 64 <480000000>;
|
|
required-opps = <&rpmhpd_opp_nom>,
|
|
<&rpmhpd_opp_nom>;
|
|
};
|
|
|
|
opp-533333334 {
|
|
opp-hz = /bits/ 64 <533333334>;
|
|
required-opps = <&rpmhpd_opp_turbo>,
|
|
<&rpmhpd_opp_turbo>;
|
|
};
|
|
};
|
|
};
|
|
|
|
videocc: clock-controller@aaf0000 {
|
|
compatible = "qcom,sm8650-videocc";
|
|
reg = <0 0x0aaf0000 0 0x10000>;
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&gcc GCC_VIDEO_AHB_CLK>;
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
cci0: cci@ac15000 {
|
|
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
|
reg = <0 0x0ac15000 0 0x1000>;
|
|
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
|
|
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
|
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
|
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
|
<&camcc CAM_CC_CCI_0_CLK>;
|
|
clock-names = "camnoc_axi",
|
|
"cpas_ahb",
|
|
"cci";
|
|
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
|
|
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
|
|
pinctrl-names = "default", "sleep";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cci0_i2c0: i2c-bus@0 {
|
|
reg = <0>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
cci0_i2c1: i2c-bus@1 {
|
|
reg = <1>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
cci1: cci@ac16000 {
|
|
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
|
reg = <0 0x0ac16000 0 0x1000>;
|
|
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>;
|
|
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
|
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
|
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
|
<&camcc CAM_CC_CCI_1_CLK>;
|
|
clock-names = "camnoc_axi",
|
|
"cpas_ahb",
|
|
"cci";
|
|
pinctrl-0 = <&cci1_0_default &cci1_1_default>;
|
|
pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
|
|
pinctrl-names = "default", "sleep";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cci1_i2c0: i2c-bus@0 {
|
|
reg = <0>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
cci1_i2c1: i2c-bus@1 {
|
|
reg = <1>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
cci2: cci@ac17000 {
|
|
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
|
reg = <0 0x0ac17000 0 0x1000>;
|
|
interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>;
|
|
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
|
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
|
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
|
<&camcc CAM_CC_CCI_2_CLK>;
|
|
clock-names = "camnoc_axi",
|
|
"cpas_ahb",
|
|
"cci";
|
|
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
|
|
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
|
|
pinctrl-names = "default", "sleep";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cci2_i2c0: i2c-bus@0 {
|
|
reg = <0>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
cci2_i2c1: i2c-bus@1 {
|
|
reg = <1>;
|
|
clock-frequency = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,sm8650-camcc";
|
|
reg = <0 0x0ade0000 0 0x20000>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
|
<&bi_tcxo_div2>,
|
|
<&bi_tcxo_ao_div2>,
|
|
<&sleep_clk>;
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
mdss: display-subsystem@ae00000 {
|
|
compatible = "qcom,sm8650-mdss";
|
|
reg = <0 0x0ae00000 0 0x1000>;
|
|
reg-names = "mdss";
|
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
|
|
|
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
|
|
|
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "mdp0-mem",
|
|
"cpu-cfg";
|
|
|
|
power-domains = <&dispcc MDSS_GDSC>;
|
|
|
|
iommus = <&apps_smmu 0x1c00 0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
mdss_mdp: display-controller@ae01000 {
|
|
compatible = "qcom,sm8650-dpu";
|
|
reg = <0 0x0ae01000 0 0x8f000>,
|
|
<0 0x0aeb0000 0 0x3000>;
|
|
reg-names = "mdp",
|
|
"vbif";
|
|
|
|
interrupts-extended = <&mdss 0>;
|
|
|
|
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
clock-names = "nrt_bus",
|
|
"iface",
|
|
"lut",
|
|
"core",
|
|
"vsync";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
operating-points-v2 = <&mdp_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
dpu_intf1_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
dpu_intf2_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi1_in>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
dpu_intf0_out: endpoint {
|
|
remote-endpoint = <&mdss_dp0_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-325000000 {
|
|
opp-hz = /bits/ 64 <325000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-375000000 {
|
|
opp-hz = /bits/ 64 <375000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-514000000 {
|
|
opp-hz = /bits/ 64 <514000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0: dsi@ae94000 {
|
|
compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0 0x0ae94000 0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupts-extended = <&mdss 4>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
|
|
phys = <&mdss_dsi0_phy>;
|
|
phy-names = "dsi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dsi0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf1_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dsi0_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-187500000 {
|
|
opp-hz = /bits/ 64 <187500000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-358000000 {
|
|
opp-hz = /bits/ 64 <358000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0_phy: phy@ae95000 {
|
|
compatible = "qcom,sm8650-dsi-phy-4nm";
|
|
reg = <0 0x0ae95000 0 0x200>,
|
|
<0 0x0ae95200 0 0x280>,
|
|
<0 0x0ae95500 0 0x400>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface",
|
|
"ref";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss_dsi1: dsi@ae96000 {
|
|
compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0 0x0ae96000 0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupts-extended = <&mdss 5>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
|
|
phys = <&mdss_dsi1_phy>;
|
|
phy-names = "dsi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dsi1_in: endpoint {
|
|
remote-endpoint = <&dpu_intf2_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dsi1_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1_phy: phy@ae97000 {
|
|
compatible = "qcom,sm8650-dsi-phy-4nm";
|
|
reg = <0 0x0ae97000 0 0x200>,
|
|
<0 0x0ae97200 0 0x280>,
|
|
<0 0x0ae97500 0 0x400>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface",
|
|
"ref";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss_dp0: displayport-controller@af54000 {
|
|
compatible = "qcom,sm8650-dp";
|
|
reg = <0 0xaf54000 0 0x104>,
|
|
<0 0xaf54200 0 0xc0>,
|
|
<0 0xaf55000 0 0x770>,
|
|
<0 0xaf56000 0 0x9c>,
|
|
<0 0xaf57000 0 0x9c>;
|
|
|
|
interrupts-extended = <&mdss 12>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
|
clock-names = "core_iface",
|
|
"core_aux",
|
|
"ctrl_link",
|
|
"ctrl_link_iface",
|
|
"stream_pixel";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
|
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
|
|
|
operating-points-v2 = <&dp_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
|
|
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
|
phy-names = "dp";
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
dp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-162000000 {
|
|
opp-hz = /bits/ 64 <162000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
|
};
|
|
|
|
opp-270000000 {
|
|
opp-hz = /bits/ 64 <270000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-540000000 {
|
|
opp-hz = /bits/ 64 <540000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-810000000 {
|
|
opp-hz = /bits/ 64 <810000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dp0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dp0_out: endpoint {
|
|
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sm8650-dispcc";
|
|
reg = <0 0x0af00000 0 0x20000>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&bi_tcxo_ao_div2>,
|
|
<&gcc GCC_DISP_AHB_CLK>,
|
|
<&sleep_clk>,
|
|
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
|
<0>, /* dp1 */
|
|
<0>,
|
|
<0>, /* dp2 */
|
|
<0>,
|
|
<0>, /* dp3 */
|
|
<0>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
usb_1_hsphy: phy@88e3000 {
|
|
compatible = "qcom,sm8650-snps-eusb2-phy",
|
|
"qcom,sm8550-snps-eusb2-phy";
|
|
reg = <0 0x088e3000 0 0x154>;
|
|
|
|
clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_dp_qmpphy: phy@88e8000 {
|
|
compatible = "qcom,sm8650-qmp-usb3-dp-phy";
|
|
reg = <0 0x088e8000 0 0x3000>;
|
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"ref",
|
|
"com_aux",
|
|
"usb3_pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
|
|
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
|
|
reset-names = "phy",
|
|
"common";
|
|
|
|
power-domains = <&gcc USB3_PHY_GDSC>;
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <1>;
|
|
|
|
orientation-switch;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
usb_dp_qmpphy_out: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
usb_dp_qmpphy_usb_ss_in: endpoint {
|
|
remote-endpoint = <&usb_1_dwc3_ss>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
usb_dp_qmpphy_dp_in: endpoint {
|
|
remote-endpoint = <&mdss_dp0_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_1: usb@a6f8800 {
|
|
compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a6f8800 0 0x400>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
|
|
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
|
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"hs_phy_irq",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&tcsr TCSR_USB3_CLKREF_EN>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"xo";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "usb-ddr",
|
|
"apps-usb";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
usb_1_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a600000 0 0xcd00>;
|
|
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
iommus = <&apps_smmu 0x40 0>;
|
|
|
|
phys = <&usb_1_hsphy>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
|
|
phy-names = "usb2-phy",
|
|
"usb3-phy";
|
|
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,usb2-gadget-lpm-disable;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,usb3_lpm_capable;
|
|
snps,usb2-lpm-disable;
|
|
snps,has-lpm-erratum;
|
|
tx-fifo-resize;
|
|
|
|
dma-coherent;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
usb_1_dwc3_hs: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
usb_1_dwc3_ss: endpoint {
|
|
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm8650-pdc", "qcom,pdc";
|
|
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
|
|
<125 63 1>, <126 716 12>,
|
|
<138 251 5>, <143 244 4>;
|
|
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tsens0: thermal-sensor@c228000 {
|
|
compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
|
|
reg = <0 0x0c228000 0 0x1000>, /* TM */
|
|
<0 0x0c222000 0 0x1000>; /* SROT */
|
|
|
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <15>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal-sensor@c229000 {
|
|
compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
|
|
reg = <0 0x0c229000 0 0x1000>, /* TM */
|
|
<0 0x0c223000 0 0x1000>; /* SROT */
|
|
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <16>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens2: thermal-sensor@c22a000 {
|
|
compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
|
|
reg = <0 0x0c22a000 0 0x1000>, /* TM */
|
|
<0 0x0c224000 0 0x1000>; /* SROT */
|
|
|
|
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <13>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-management@c300000 {
|
|
compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
|
|
reg = <0 0x0c300000 0 0x400>;
|
|
|
|
interrupt-parent = <&ipcc>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats";
|
|
reg = <0 0x0c3f0000 0 0x400>;
|
|
qcom,qmp = <&aoss_qmp>;
|
|
};
|
|
|
|
spmi_bus: spmi@c400000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0 0x0c400000 0 0x3000>,
|
|
<0 0x0c500000 0 0x400000>,
|
|
<0 0x0c440000 0 0x80000>,
|
|
<0 0x0c4c0000 0 0x20000>,
|
|
<0 0x0c42d000 0 0x4000>;
|
|
reg-names = "core",
|
|
"chnls",
|
|
"obsrvr",
|
|
"intr",
|
|
"cnfg";
|
|
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,bus-id = <0>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
tlmm: pinctrl@f100000 {
|
|
compatible = "qcom,sm8650-tlmm";
|
|
reg = <0 0x0f100000 0 0x300000>;
|
|
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
gpio-ranges = <&tlmm 0 0 211>;
|
|
|
|
wakeup-parent = <&pdc>;
|
|
|
|
cci0_0_default: cci0-0-default-state {
|
|
sda-pins {
|
|
pins = "gpio113";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio114";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci0_0_sleep: cci0-0-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio113";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio114";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
cci0_1_default: cci0-1-default-state {
|
|
sda-pins {
|
|
pins = "gpio115";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio116";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci0_1_sleep: cci0-1-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio115";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio116";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
cci1_0_default: cci1-0-default-state {
|
|
sda-pins {
|
|
pins = "gpio117";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio118";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci1_0_sleep: cci1-0-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio117";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio118";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
cci1_1_default: cci1-1-default-state {
|
|
sda-pins {
|
|
pins = "gpio12";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio13";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci1_1_sleep: cci1-1-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio12";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio13";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
cci2_0_default: cci2-0-default-state {
|
|
sda-pins {
|
|
pins = "gpio112";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio153";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci2_0_sleep: cci2-0-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio112";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio153";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
cci2_1_default: cci2-1-default-state {
|
|
sda-pins {
|
|
pins = "gpio119";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio120";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-up = <2200>;
|
|
};
|
|
};
|
|
|
|
cci2_1_sleep: cci2-1-sleep-state {
|
|
sda-pins {
|
|
pins = "gpio119";
|
|
function = "cci_i2c_sda";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
scl-pins {
|
|
pins = "gpio120";
|
|
function = "cci_i2c_scl";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio64", "gpio65";
|
|
function = "i2chub0_se0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c1_data_clk: hub-i2c1-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio66", "gpio67";
|
|
function = "i2chub0_se1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c2_data_clk: hub-i2c2-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio68", "gpio69";
|
|
function = "i2chub0_se2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c3_data_clk: hub-i2c3-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio70", "gpio71";
|
|
function = "i2chub0_se3";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c4_data_clk: hub-i2c4-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio72", "gpio73";
|
|
function = "i2chub0_se4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c5_data_clk: hub-i2c5-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio74", "gpio75";
|
|
function = "i2chub0_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c6_data_clk: hub-i2c6-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio76", "gpio77";
|
|
function = "i2chub0_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c7_data_clk: hub-i2c7-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio78", "gpio79";
|
|
function = "i2chub0_se7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c8_data_clk: hub-i2c8-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio206", "gpio207";
|
|
function = "i2chub0_se8";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
hub_i2c9_data_clk: hub-i2c9-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio80", "gpio81";
|
|
function = "i2chub0_se9";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcie0_default_state: pcie0-default-state {
|
|
perst-pins {
|
|
pins = "gpio94";
|
|
function = "gpio";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
clkreq-pins {
|
|
pins = "gpio95";
|
|
function = "pcie0_clk_req_n";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
wake-pins {
|
|
pins = "gpio96";
|
|
function = "gpio";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_default_state: pcie1-default-state {
|
|
perst-pins {
|
|
pins = "gpio97";
|
|
function = "gpio";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
clkreq-pins {
|
|
pins = "gpio98";
|
|
function = "pcie1_clk_req_n";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
wake-pins {
|
|
pins = "gpio99";
|
|
function = "gpio";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio32", "gpio33";
|
|
function = "qup1_se0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup1_se1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio40", "gpio41";
|
|
function = "qup1_se2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio44", "gpio45";
|
|
function = "qup1_se3";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio48", "gpio49";
|
|
function = "qup1_se4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio52", "gpio53";
|
|
function = "qup1_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio56", "gpio57";
|
|
function = "qup1_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio60", "gpio61";
|
|
function = "qup1_se7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup2_se0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c9_data_clk: qup-i2c9-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup2_se1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio8", "gpio9";
|
|
function = "qup2_se2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio12", "gpio13";
|
|
function = "qup2_se3";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio16", "gpio17";
|
|
function = "qup2_se4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio20", "gpio21";
|
|
function = "qup2_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c14_data_clk: qup-i2c14-data-clk-state {
|
|
/* SDA, SCL */
|
|
pins = "gpio24", "gpio25";
|
|
function = "qup2_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi0_cs: qup-spi0-cs-state {
|
|
pins = "gpio35";
|
|
function = "qup1_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi0_data_clk: qup-spi0-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio32", "gpio33", "gpio34";
|
|
function = "qup1_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi1_cs: qup-spi1-cs-state {
|
|
pins = "gpio39";
|
|
function = "qup1_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi1_data_clk: qup-spi1-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio36", "gpio37", "gpio38";
|
|
function = "qup1_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi2_cs: qup-spi2-cs-state {
|
|
pins = "gpio43";
|
|
function = "qup1_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi2_data_clk: qup-spi2-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio40", "gpio41", "gpio42";
|
|
function = "qup1_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi3_cs: qup-spi3-cs-state {
|
|
pins = "gpio47";
|
|
function = "qup1_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi3_data_clk: qup-spi3-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio44", "gpio45", "gpio46";
|
|
function = "qup1_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi4_cs: qup-spi4-cs-state {
|
|
pins = "gpio51";
|
|
function = "qup1_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi4_data_clk: qup-spi4-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio48", "gpio49", "gpio50";
|
|
function = "qup1_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi5_cs: qup-spi5-cs-state {
|
|
pins = "gpio55";
|
|
function = "qup1_se5";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi5_data_clk: qup-spi5-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio52", "gpio53", "gpio54";
|
|
function = "qup1_se5";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi6_cs: qup-spi6-cs-state {
|
|
pins = "gpio59";
|
|
function = "qup1_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi6_data_clk: qup-spi6-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio56", "gpio57", "gpio58";
|
|
function = "qup1_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi7_cs: qup-spi7-cs-state {
|
|
pins = "gpio63";
|
|
function = "qup1_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi7_data_clk: qup-spi7-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio60", "gpio61", "gpio62";
|
|
function = "qup1_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi8_cs: qup-spi8-cs-state {
|
|
pins = "gpio3";
|
|
function = "qup2_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi8_data_clk: qup-spi8-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio0", "gpio1", "gpio2";
|
|
function = "qup2_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi9_cs: qup-spi9-cs-state {
|
|
pins = "gpio7";
|
|
function = "qup2_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi9_data_clk: qup-spi9-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio4", "gpio5", "gpio6";
|
|
function = "qup2_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi10_cs: qup-spi10-cs-state {
|
|
pins = "gpio11";
|
|
function = "qup2_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi10_data_clk: qup-spi10-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio8", "gpio9", "gpio10";
|
|
function = "qup2_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi11_cs: qup-spi11-cs-state {
|
|
pins = "gpio15";
|
|
function = "qup2_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi11_data_clk: qup-spi11-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio12", "gpio13", "gpio14";
|
|
function = "qup2_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi12_cs: qup-spi12-cs-state {
|
|
pins = "gpio19";
|
|
function = "qup2_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi12_data_clk: qup-spi12-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio16", "gpio17", "gpio18";
|
|
function = "qup2_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi13_cs: qup-spi13-cs-state {
|
|
pins = "gpio23";
|
|
function = "qup2_se5";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi13_data_clk: qup-spi13-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio20", "gpio21", "gpio22";
|
|
function = "qup2_se5";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi14_cs: qup-spi14-cs-state {
|
|
pins = "gpio27";
|
|
function = "qup2_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi14_data_clk: qup-spi14-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio24", "gpio25", "gpio26";
|
|
function = "qup2_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_uart14_default: qup-uart14-default-state {
|
|
/* TX, RX */
|
|
pins = "gpio26", "gpio27";
|
|
function = "qup2_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_uart14_cts_rts: qup-uart14-cts-rts-state {
|
|
/* CTS, RTS */
|
|
pins = "gpio24", "gpio25";
|
|
function = "qup2_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
qup_uart15_default: qup-uart15-default-state {
|
|
/* TX, RX */
|
|
pins = "gpio30", "gpio31";
|
|
function = "qup2_se7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
sdc2_sleep: sdc2-sleep-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_default: sdc2-default-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10042000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
|
|
reg = <0x0 0x10042000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
|
|
funnel_in1_in_funnel_apss: endpoint {
|
|
remote-endpoint = <&funnel_apss_out_funnel_in1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_in1_out_funnel_qdss: endpoint {
|
|
remote-endpoint = <&funnel_qdss_in_funnel_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10045000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
|
|
reg = <0x0 0x10045000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
funnel_qdss_in_funnel_in1: endpoint {
|
|
remote-endpoint = <&funnel_in1_out_funnel_qdss>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_qdss_out_funnel_aoss: endpoint {
|
|
remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b04000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
|
|
reg = <0x0 0x10b04000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
|
|
funnel_aoss_in_funnel_qdss: endpoint {
|
|
remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_aoss_out_tmc_etf: endpoint {
|
|
remote-endpoint = <&tmc_etf_in_funnel_aoss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@10b05000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
|
|
reg = <0x0 0x10b05000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
tmc_etf_in_funnel_aoss: endpoint {
|
|
remote-endpoint = <&funnel_aoss_out_tmc_etf>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13810000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
|
|
reg = <0x0 0x13810000 0x0 0x1000>;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
funnel_apss_in_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_out_funnel_apss>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_apss_out_funnel_in1: endpoint {
|
|
remote-endpoint = <&funnel_in1_in_funnel_apss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0 0x15000000 0 0x100000>;
|
|
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <1>;
|
|
|
|
dma-coherent;
|
|
};
|
|
|
|
intc: interrupt-controller@17100000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0 0x17100000 0 0x10000>, /* GICD */
|
|
<0 0x17180000 0 0x200000>; /* GICR * 8 */
|
|
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
|
|
|
|
#interrupt-cells = <4>;
|
|
interrupt-controller;
|
|
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0 0x40000>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
ppi-partitions {
|
|
ppi_cluster0: interrupt-partition-0 {
|
|
affinity = <&cpu0 &cpu1>;
|
|
};
|
|
|
|
ppi_cluster1: interrupt-partition-1 {
|
|
affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>;
|
|
};
|
|
|
|
ppi_cluster2: interrupt-partition-2 {
|
|
affinity = <&cpu7>;
|
|
};
|
|
};
|
|
|
|
gic_its: msi-controller@17140000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0 0x17140000 0 0x20000>;
|
|
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
};
|
|
};
|
|
|
|
timer@17420000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0 0x17420000 0 0x1000>;
|
|
|
|
ranges = <0 0 0 0x20000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
frame@17421000 {
|
|
reg = <0x17421000 0x1000>,
|
|
<0x17422000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <0>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
reg = <0x17423000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
reg = <0x17425000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <2>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
reg = <0x17427000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <3>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
reg = <0x17429000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
reg = <0x1742b000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <5>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
reg = <0x1742d000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
frame-number = <6>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17a00000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0 0x17a00000 0 0x10000>,
|
|
<0 0x17a10000 0 0x10000>,
|
|
<0 0x17a20000 0 0x10000>;
|
|
reg-names = "drv-0",
|
|
"drv-1",
|
|
"drv-2";
|
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
power-domains = <&cluster_pd>;
|
|
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>, <CONTROL_TCS 0>;
|
|
|
|
label = "apps_rsc";
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8650-rpmh-clk";
|
|
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sm8650-rpmhpd";
|
|
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
#power-domain-cells = <1>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp-16 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp-48 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d2: opp-52 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d1: opp-56 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d0: opp-60 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp-64 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_l1: opp-80 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp-128 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l0: opp-144 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp-192 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp-256 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp-320 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp-336 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp-384 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp-416 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
epss_l3: interconnect@17d90000 {
|
|
compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3";
|
|
reg = <0 0x17d90000 0 0x1000>;
|
|
|
|
clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@17d91000 {
|
|
compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0 0x17d91000 0 0x1000>,
|
|
<0 0x17d92000 0 0x1000>,
|
|
<0 0x17d93000 0 0x1000>,
|
|
<0 0x17d94000 0 0x1000>;
|
|
reg-names = "freq-domain0",
|
|
"freq-domain1",
|
|
"freq-domain2",
|
|
"freq-domain3";
|
|
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "dcvsh-irq-0",
|
|
"dcvsh-irq-1",
|
|
"dcvsh-irq-2",
|
|
"dcvsh-irq-3";
|
|
|
|
clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pmu@24091000 {
|
|
compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
|
|
reg = <0 0x24091000 0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
|
|
operating-points-v2 = <&llcc_bwmon_opp_table>;
|
|
|
|
llcc_bwmon_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-0 {
|
|
opp-peak-kBps = <2086000>;
|
|
};
|
|
|
|
opp-1 {
|
|
opp-peak-kBps = <2929000>;
|
|
};
|
|
|
|
opp-2 {
|
|
opp-peak-kBps = <5931000>;
|
|
};
|
|
|
|
opp-3 {
|
|
opp-peak-kBps = <6515000>;
|
|
};
|
|
|
|
opp-4 {
|
|
opp-peak-kBps = <7980000>;
|
|
};
|
|
|
|
opp-5 {
|
|
opp-peak-kBps = <10437000>;
|
|
};
|
|
|
|
opp-6 {
|
|
opp-peak-kBps = <12157000>;
|
|
};
|
|
|
|
opp-7 {
|
|
opp-peak-kBps = <14060000>;
|
|
};
|
|
|
|
opp-8 {
|
|
opp-peak-kBps = <16113000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmu@240b7400 {
|
|
compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
|
|
reg = <0 0x240b7400 0 0x600>;
|
|
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
|
|
operating-points-v2 = <&cpu_bwmon_opp_table>;
|
|
|
|
cpu_bwmon_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-0 {
|
|
opp-peak-kBps = <4577000>;
|
|
};
|
|
|
|
opp-1 {
|
|
opp-peak-kBps = <7110000>;
|
|
};
|
|
|
|
opp-2 {
|
|
opp-peak-kBps = <9155000>;
|
|
};
|
|
|
|
opp-3 {
|
|
opp-peak-kBps = <12298000>;
|
|
};
|
|
|
|
opp-4 {
|
|
opp-peak-kBps = <14236000>;
|
|
};
|
|
|
|
opp-5 {
|
|
opp-peak-kBps = <16265000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gem_noc: interconnect@24100000 {
|
|
compatible = "qcom,sm8650-gem-noc";
|
|
reg = <0 0x24100000 0 0xc5080>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
system-cache-controller@25000000 {
|
|
compatible = "qcom,sm8650-llcc";
|
|
reg = <0 0x25000000 0 0x200000>,
|
|
<0 0x25400000 0 0x200000>,
|
|
<0 0x25200000 0 0x200000>,
|
|
<0 0x25600000 0 0x200000>,
|
|
<0 0x25800000 0 0x200000>,
|
|
<0 0x25a00000 0 0x200000>;
|
|
reg-names = "llcc0_base",
|
|
"llcc1_base",
|
|
"llcc2_base",
|
|
"llcc3_base",
|
|
"llcc_broadcast_base",
|
|
"llcc_broadcast_and_base";
|
|
|
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
nsp_noc: interconnect@320c0000 {
|
|
compatible = "qcom,sm8650-nsp-noc";
|
|
reg = <0 0x320c0000 0 0xf080>;
|
|
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
remoteproc_cdsp: remoteproc@32300000 {
|
|
compatible = "qcom,sm8650-cdsp-pas";
|
|
reg = <0x0 0x32300000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
|
|
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"ready",
|
|
"handover",
|
|
"stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>,
|
|
<&rpmhpd RPMHPD_MXC>,
|
|
<&rpmhpd RPMHPD_NSP>;
|
|
power-domain-names = "cx",
|
|
"mxc",
|
|
"nsp";
|
|
|
|
memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_cdsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
qcom,remote-pid = <5>;
|
|
|
|
label = "cdsp";
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
|
|
label = "cdsp";
|
|
|
|
qcom,non-secure-domain;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@1 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <1>;
|
|
|
|
iommus = <&apps_smmu 0x1961 0x0>,
|
|
<&apps_smmu 0x0c01 0x20>,
|
|
<&apps_smmu 0x19c1 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@2 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <2>;
|
|
|
|
iommus = <&apps_smmu 0x1962 0x0>,
|
|
<&apps_smmu 0x0c02 0x20>,
|
|
<&apps_smmu 0x19c2 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
|
|
iommus = <&apps_smmu 0x1963 0x0>,
|
|
<&apps_smmu 0x0c03 0x20>,
|
|
<&apps_smmu 0x19c3 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
|
|
iommus = <&apps_smmu 0x1964 0x0>,
|
|
<&apps_smmu 0x0c04 0x20>,
|
|
<&apps_smmu 0x19c4 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
|
|
iommus = <&apps_smmu 0x1965 0x0>,
|
|
<&apps_smmu 0x0c05 0x20>,
|
|
<&apps_smmu 0x19c5 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@6 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <6>;
|
|
|
|
iommus = <&apps_smmu 0x1966 0x0>,
|
|
<&apps_smmu 0x0c06 0x20>,
|
|
<&apps_smmu 0x19c6 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@7 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <7>;
|
|
|
|
iommus = <&apps_smmu 0x1967 0x0>,
|
|
<&apps_smmu 0x0c07 0x20>,
|
|
<&apps_smmu 0x19c7 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@8 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <8>;
|
|
|
|
iommus = <&apps_smmu 0x1968 0x0>,
|
|
<&apps_smmu 0x0c08 0x20>,
|
|
<&apps_smmu 0x19c8 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
/* note: secure cb9 in downstream */
|
|
|
|
compute-cb@12 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <12>;
|
|
|
|
iommus = <&apps_smmu 0x196c 0x0>,
|
|
<&apps_smmu 0x0c0c 0x20>,
|
|
<&apps_smmu 0x19cc 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@13 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <13>;
|
|
|
|
iommus = <&apps_smmu 0x196d 0x0>,
|
|
<&apps_smmu 0x0c0d 0x20>,
|
|
<&apps_smmu 0x19cd 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
compute-cb@14 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <14>;
|
|
|
|
iommus = <&apps_smmu 0x196e 0x0>,
|
|
<&apps_smmu 0x0c0e 0x20>,
|
|
<&apps_smmu 0x19ce 0x0>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
aoss0-thermal {
|
|
thermal-sensors = <&tsens0 0>;
|
|
|
|
trips {
|
|
aoss0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss0-thermal {
|
|
thermal-sensors = <&tsens0 1>;
|
|
|
|
trips {
|
|
cpuss0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss1-thermal {
|
|
thermal-sensors = <&tsens0 2>;
|
|
|
|
trips {
|
|
cpuss1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss2-thermal {
|
|
thermal-sensors = <&tsens0 3>;
|
|
|
|
trips {
|
|
cpuss2-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss2-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss3-thermal {
|
|
thermal-sensors = <&tsens0 4>;
|
|
|
|
trips {
|
|
cpuss3-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss3-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-top-thermal {
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
cpu2-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-bottom-thermal {
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
cpu2-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-top-thermal {
|
|
thermal-sensors = <&tsens0 7>;
|
|
|
|
trips {
|
|
cpu3-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-bottom-thermal {
|
|
thermal-sensors = <&tsens0 8>;
|
|
|
|
trips {
|
|
cpu3-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-top-thermal {
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
cpu4-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-bottom-thermal {
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
cpu4-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-top-thermal {
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
cpu5-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-bottom-thermal {
|
|
thermal-sensors = <&tsens0 12>;
|
|
|
|
trips {
|
|
cpu5-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-top-thermal {
|
|
thermal-sensors = <&tsens0 13>;
|
|
|
|
trips {
|
|
cpu6-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-bottom-thermal {
|
|
thermal-sensors = <&tsens0 14>;
|
|
|
|
trips {
|
|
cpu6-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss1-thermal {
|
|
thermal-sensors = <&tsens1 0>;
|
|
|
|
trips {
|
|
aoss1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-top-thermal {
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
cpu7-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-middle-thermal {
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
cpu7-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-bottom-thermal {
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
cpu7-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0-thermal {
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
cpu0-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
cpu1-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx0-thermal {
|
|
thermal-sensors = <&tsens2 6>;
|
|
|
|
trips {
|
|
nsphvx0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphvx0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx1-thermal {
|
|
thermal-sensors = <&tsens2 7>;
|
|
|
|
trips {
|
|
nsphvx1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphvx1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx0-thermal {
|
|
thermal-sensors = <&tsens2 8>;
|
|
|
|
trips {
|
|
nsphmx0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx1-thermal {
|
|
thermal-sensors = <&tsens2 9>;
|
|
|
|
trips {
|
|
nsphmx1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx2-thermal {
|
|
thermal-sensors = <&tsens2 10>;
|
|
|
|
trips {
|
|
nsphmx2-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx2-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx3-thermal {
|
|
thermal-sensors = <&tsens2 11>;
|
|
|
|
trips {
|
|
nsphmx3-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx3-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-thermal {
|
|
thermal-sensors = <&tsens1 12>;
|
|
|
|
trips {
|
|
video-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
video-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr-thermal {
|
|
thermal-sensors = <&tsens1 13>;
|
|
|
|
trips {
|
|
ddr-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
ddr-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera0-thermal {
|
|
thermal-sensors = <&tsens1 14>;
|
|
|
|
trips {
|
|
camera0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
camera0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera1-thermal {
|
|
thermal-sensors = <&tsens1 15>;
|
|
|
|
trips {
|
|
camera1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
camera1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss2-thermal {
|
|
thermal-sensors = <&tsens2 0>;
|
|
|
|
trips {
|
|
aoss2-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss2-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 1>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu0_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu0_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 2>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu1_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu1_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss2-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 3>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu2_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu2_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss3-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 4>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu3_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu3_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss4-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 5>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu4_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu4_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss5-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 6>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu5_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu5_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss6-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 7>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu6_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu6_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss7-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens2 8>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu7_alert0>;
|
|
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
gpu7_alert0: trip-point0 {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
trip-point2 {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem0-thermal {
|
|
thermal-sensors = <&tsens2 9>;
|
|
|
|
trips {
|
|
modem0-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem0-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem1-thermal {
|
|
thermal-sensors = <&tsens2 10>;
|
|
|
|
trips {
|
|
modem1-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem1-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2-thermal {
|
|
thermal-sensors = <&tsens2 11>;
|
|
|
|
trips {
|
|
modem2-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem2-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem3-thermal {
|
|
thermal-sensors = <&tsens2 12>;
|
|
|
|
trips {
|
|
modem3-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem3-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
|
|
};
|
|
};
|