mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 08:32:55 +00:00
8e7e63fc47
The Arm GIC "ppi-partitions" node is only relevant to GICv3 and makes no sense for GICv2 implementations which the GIC-400 is. PPIs in GICv2 have no CPU affinity. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250609203721.2852879-1-robh@kernel.org Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/r/20250710-nuvoton-arm64-dt-v1-1-ec7db96ea507@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
240 lines
6.2 KiB
Plaintext
240 lines
6.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
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#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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gcr: system-controller@f0800000 {
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compatible = "nuvoton,npcm845-gcr", "syscon";
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reg = <0x0 0xf0800000 0x0 0x1000>;
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};
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gic: interrupt-controller@dfff9000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xdfff9000 0x0 0x1000>,
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<0x0 0xdfffa000 0x0 0x2000>,
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<0x0 0xdfffc000 0x0 0x2000>,
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<0x0 0xdfffe000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <0>;
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};
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};
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ahb {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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rstc: reset-controller@f0801000 {
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compatible = "nuvoton,npcm845-reset";
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reg = <0x0 0xf0801000 0x0 0x78>;
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#reset-cells = <2>;
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nuvoton,sysgcr = <&gcr>;
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};
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm845-clk";
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#clock-cells = <1>;
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reg = <0x0 0xf0801000 0x0 0x1000>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf0000000 0x00300000>,
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<0xfff00000 0x0 0xfff00000 0x00016000>;
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peci: peci-controller@100000 {
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compatible = "nuvoton,npcm845-peci";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM8XX_CLK_APB3>;
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cmd-timeout-ms = <1000>;
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status = "disabled";
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};
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timer0: timer@8000 {
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compatible = "nuvoton,npcm845-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x1C>;
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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clock-names = "refclk";
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};
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serial0: serial@0 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x0 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial1: serial@1000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x1000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial2: serial@2000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x2000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial3: serial@3000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x3000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial4: serial@4000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x4000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial5: serial@5000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x5000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial6: serial@6000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x6000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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watchdog0: watchdog@801c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x801c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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watchdog1: watchdog@901c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x901c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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watchdog2: watchdog@a01c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xa01c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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};
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};
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pinctrl: pinctrl@f0010000 {
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compatible = "nuvoton,npcm845-pinctrl";
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ranges = <0x0 0x0 0xf0010000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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nuvoton,sysgcr = <&gcr>;
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status = "okay";
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gpio0: gpio@f0010000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0xB0>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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gpio1: gpio@f0011000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0xB0>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 32 32>;
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};
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gpio2: gpio@f0012000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2000 0xB0>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 64 32>;
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};
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gpio3: gpio@f0013000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x3000 0xB0>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 96 32>;
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};
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gpio4: gpio@f0014000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x4000 0xB0>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 128 32>;
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};
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gpio5: gpio@f0015000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x5000 0xB0>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 160 32>;
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};
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gpio6: gpio@f0016000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x6000 0xB0>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 192 32>;
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};
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gpio7: gpio@f0017000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x7000 0xB0>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 224 32>;
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};
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};
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};
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