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Add MT8195 UFSHCI compatible string. Relax the schema to allow between one to eight clocks/clock-names entries for all MediaTek UFS nodes. Legacy platforms may only need a few clocks, whereas newer devices such as the MT8195 require additional clock-gating domains. For MT8195 specifically, enforce exactly eight clocks and clock-names entries to satisfy its hardware requirements. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://lore.kernel.org/r/20250722085721.2062657-3-macpaul.lin@mediatek.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
102 lines
2.0 KiB
YAML
102 lines
2.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek Universal Flash Storage (UFS) Controller
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maintainers:
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- Stanley Chu <stanley.chu@mediatek.com>
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properties:
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compatible:
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enum:
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- mediatek,mt8183-ufshci
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- mediatek,mt8192-ufshci
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- mediatek,mt8195-ufshci
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clocks:
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minItems: 1
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maxItems: 8
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clock-names:
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minItems: 1
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maxItems: 8
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phys:
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maxItems: 1
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reg:
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maxItems: 1
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vcc-supply: true
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mediatek,ufs-disable-mcq:
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$ref: /schemas/types.yaml#/definitions/flag
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description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
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required:
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- compatible
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- clocks
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- clock-names
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- phys
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- reg
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- vcc-supply
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unevaluatedProperties: false
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allOf:
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- $ref: ufs-common.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8195-ufshci
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then:
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properties:
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clocks:
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minItems: 8
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clock-names:
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items:
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- const: ufs
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- const: ufs_aes
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- const: ufs_tick
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- const: unipro_sysclk
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- const: unipro_tick
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- const: unipro_mp_bclk
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- const: ufs_tx_symbol
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- const: ufs_mem_sub
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: ufs
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@ff3c0000 {
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compatible = "mediatek,mt8183-ufshci";
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reg = <0 0x11270000 0 0x2300>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
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phys = <&ufsphy>;
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clocks = <&infracfg_ao CLK_INFRA_UFS>;
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clock-names = "ufs";
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freq-table-hz = <0 0>;
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vcc-supply = <&mt_pmic_vemc_ldo_reg>;
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};
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};
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