# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Universal Flash Storage (UFS) Controller

maintainers:
  - Stanley Chu <stanley.chu@mediatek.com>

properties:
  compatible:
    enum:
      - mediatek,mt8183-ufshci
      - mediatek,mt8192-ufshci
      - mediatek,mt8195-ufshci

  clocks:
    minItems: 1
    maxItems: 8

  clock-names:
    minItems: 1
    maxItems: 8

  phys:
    maxItems: 1

  reg:
    maxItems: 1

  vcc-supply: true

  mediatek,ufs-disable-mcq:
    $ref: /schemas/types.yaml#/definitions/flag
    description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.

required:
  - compatible
  - clocks
  - clock-names
  - phys
  - reg
  - vcc-supply

unevaluatedProperties: false

allOf:
  - $ref: ufs-common.yaml

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8195-ufshci
    then:
      properties:
        clocks:
          minItems: 8
        clock-names:
          items:
            - const: ufs
            - const: ufs_aes
            - const: ufs_tick
            - const: unipro_sysclk
            - const: unipro_tick
            - const: unipro_mp_bclk
            - const: ufs_tx_symbol
            - const: ufs_mem_sub
    else:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: ufs

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs@ff3c0000 {
            compatible = "mediatek,mt8183-ufshci";
            reg = <0 0x11270000 0 0x2300>;
            interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
            phys = <&ufsphy>;

            clocks = <&infracfg_ao CLK_INFRA_UFS>;
            clock-names = "ufs";
            freq-table-hz = <0 0>;

            vcc-supply = <&mt_pmic_vemc_ldo_reg>;
        };
    };