mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
7e5368a14b
Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
76 lines
1.9 KiB
YAML
76 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Graphics Clock & Reset Controller on SM8450
|
|
|
|
maintainers:
|
|
- Konrad Dybcio <konradybcio@kernel.org>
|
|
|
|
description: |
|
|
Qualcomm graphics clock control module provides the clocks, resets and power
|
|
domains on Qualcomm SoCs.
|
|
|
|
See also::
|
|
include/dt-bindings/clock/qcom,milos-gpucc.h
|
|
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
|
|
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
|
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
|
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
|
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
|
include/dt-bindings/reset/qcom,sm8650-gpucc.h
|
|
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- qcom,milos-gpucc
|
|
- qcom,sar2130p-gpucc
|
|
- qcom,sm4450-gpucc
|
|
- qcom,sm8450-gpucc
|
|
- qcom,sm8475-gpucc
|
|
- qcom,sm8550-gpucc
|
|
- qcom,sm8650-gpucc
|
|
- qcom,x1e80100-gpucc
|
|
- qcom,x1p42100-gpucc
|
|
|
|
clocks:
|
|
items:
|
|
- description: Board XO source
|
|
- description: GPLL0 main branch source
|
|
- description: GPLL0 div branch source
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- '#power-domain-cells'
|
|
|
|
allOf:
|
|
- $ref: qcom,gcc.yaml#
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
clock-controller@3d90000 {
|
|
compatible = "qcom,sm8450-gpucc";
|
|
reg = <0 0x03d90000 0 0xa000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
};
|
|
...
|