The 'bootph-all' tag was added to the dt-schema to describe the various
nodes used during the different phases of bootup with DT. Add the
bootph-all tag to all required nodes for all AM65x platforms.
Mark the mailbox and ring accelerators needed to communicate the with
various vendor firmware and the power, clock and reset nodes along with
the MMR for the chip-id to facilitate detecting the SoC and which
silicon version during the early stages of bootup with 'bootph-all' as
they are used during all phases of bootup
--
Changes in v2:
- removed tag from &mcu_udmap{} node
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20250710-65-boot-phases-v2-1-d431deb88783@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Now that the TI K3 AM654 system controller bindings also cover the
usage in the main domain, add its compatible to address dtbs_check
complains:
k3-am654-base-board.dtb: scm-conf@100000: compatible: ['syscon', 'simple-mfd'] is too short
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20250421214620.3770172-3-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add pa-stats nodes to k3-am65-main.dtsi for all ICSSG instances.
This is needed to dump IET related statistics for ICSSG Driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-2-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add Error Signaling Module (ESM) instances in MCU and MAIN domains,
set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt
Sources.
There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not
possible to reset the CPU using watchdog and ESM0 configuration.
However add ESM instances for device completion.
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] http://www.ti.com/lit/pdf/spruid7
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-7-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
A PRU system event "vring" has been added to each PRU and RTU
node in each of the ICSSG0, ICSSG1 and ICSSG2 remote processor
subsystems to enable the virtio/rpmsg communication between MPU
and that PRU/RTU core. The additions are done in the base
k3-am65-main.dtsi, and so are inherited by all the K3 AM65x
boards.
The PRU system events is the preferred approach over using TI
mailboxes, as it eliminates an external peripheral access from
the PRU/RTU-side, and keeps the interrupt generation internal to
the ICSSG. The difference from MPU would be minimal in using one
versus the other.
Mailboxes can still be used if desired, but currently there is
no support on firmware-side for K3 SoCs to use mailboxes. Either
approach would require that an appropriate firmware image is
loaded/booted on the PRU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://lore.kernel.org/r/20240529064420.571615-3-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD.
Remove the properties that are not applicable for each device.
Fixes: eac99d38f8 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
Fixes: d7600d070f ("arm64: dts: ti: k3-am65-main: Add support for sdhci1")
Signed-off-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20240423151732.3541894-3-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Update otap-del-sel properties as per datasheet [0].
Add missing clkbuf-sel and itap-del-sel values also as per
datasheet [0].
Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties
so the sdhci nodes could be more uniform across platforms.
[0] https://www.ti.com/lit/ds/symlink/am6548.pdf
Fixes: eac99d38f8 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
Fixes: d7600d070f ("arm64: dts: ti: k3-am65-main: Add support for sdhci1")
Signed-off-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20240423151732.3541894-2-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
These SerDes lane select muxes use bits from the same register as
the SerDes clock select mux. Make the lane select mux a child
of the SerDes control node.
This removes one more requirement on scm-conf being a syscon node
which will later be converted to fix a couple DTS check warnings.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240326185627.29852-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This matches the binding for this register region which fixes a couple
DTS check warnings.
While here trim the leading 0s from the "reg" definition.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240326185627.29852-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
As described in the binding document for the "current-speed" property:
"This should only be present in case a driver has no chance to know the
baud rate of the slave device."
This is not the case for the UART used in K3 devices, the current
baud-rate can be calculated from the registers. Having this property
has the effect of actually skipping the baud-rate setup in some drivers
as it assumes it will already be set to this rate, which may not always
be the case.
It seems this property's purpose was mistaken as selecting the desired
baud-rate, which it does not. It would have been wrong to select that
here anyway as DT is not the place for configuration, especially when
there are already more standard ways to set serial baud-rates.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240326185441.29656-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
New Features across family / New SoCs:
- J722s SoC and board support with OSPI NOR, CPSW ethernet
- Camera capture support on mulitple J7xx SoCs, AM68, AM69 and AM62P SoCs
- Wave5 Encoder/Decoder support for J721s2, J784s4 and AM62P
Generic Cleanups/Fixes:
- Stop spliting single mbox items
- Adds MIT license along with GPL-2.0 for all TI DTS files
- Moves PCIe EP nodes in overlays
- VTM Power domain fixups for J7xx SoCs
- Conversion of mmio mux users to reg-mux where possible
- Drops unnecessary UART pinmuxes on J7xx SoCs
- MMC TAP value updates for AM64/AM62A/AM62P for improved stability
- DSS register space updates for AM65/AM62/AM62A
SoC specific Fixes/Features:
J7200:
- Adds CAN support
- New compatible for J7200 to support IO wakeup
AM62A
- HDMI Display (DSS) support
- Move to simple-bus for main_conf node
- eMMC, additional MMC/SD instance support
AM62
- move to simple-bus for main_conf node
AM654
- IOT2050-SM board support
- IOT2050 DT refractoring.
AM64
- SolidRun AM642 HummingBoard-T support and its DT overlays
- ICSSG Ethernet support and associated peripherals
Board specific fixes/Features:
- Beagle Play MDIO and USB node fixes
- TPM support on k3-am642-phyboard-electra and verdin-am62-mallow
- Phycore-am64 ADC
- PCIe + USB2.0 SERDES and PCIe + USB3.0 SERDES card support
- USB1 support on verdin-am62
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmXdqWMQHHZpZ25lc2hy
QHRpLmNvbQAKCRDERh5FfJEW425kB/4spafS0XBafSITRuMy4qcIpXtoEUJoGky3
yQje7rZoM6QX2xuISUv+AydIn5JO2U/ar7UVGwY8qsKB/frq+RjvHlZLGNUynwTR
viAai3aRQv+olhUlZByWS7R8rax5f7H4dPh2a1im4bg1Ljxv1Az7NTRAFh8XzF+e
bMJgNI1Y0iCog9uf1gLig/tXAKBo4SZruE+UqC5muTfk4zUZx1je5emf+1zBb60X
en15AdoSI/8zOVil0tUmiVO582KJpfALbUK+AwExzlimeqo/PXVcgxAJKD8VxjUi
TZa2MFeZCO+D01tMk1SzVLIx/Hv5o10MOiqL8jF1HNjmIYctsV8x
=ILYz
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXiFRgACgkQYKtH/8kJ
UieNURAAycjd4jonMyCs5SxwtDMLmcXt2xSQuAs5T2D1eBj3D0CC1Fi+CDq0gizP
0sSYbMaTGs4dHXY73fGVMGMmCNhmLjVt0wArX2egzBZlskYrk4il24nZR7geNQ1w
c0bW1uoCEVP19aO8FaIfdyfRGH4V2yIeugNoaDYrh7FrdRNwJMi00G1Alx5lja4S
ZtMvZ7FVjKUCoBUccctyOkEZxrqO/uvpE6EYKUaZFMiip5hdY3CQsFic9AjAv8XF
aeW6x8w7+KDKXXOGLRG+p1J3wysP2r91WcZd0wB8gYM2R6qCZt1irYVtdDf16x65
n+i4vlRouQYqUsll18EEQPj9Pin4iv6b2jZwAl20ZzHHZzpsbp4r8Zacqw4hLOwR
gaGHck4q/Nc++CeirvF7MptIC5kWCXu2+McKjx2bavM2C2p3ezhWQpo4Cbu2v93t
SvEQir25SvFJ1Y48S27nDPgRqt8dCMNCuatKbAPpqi1/jbwqi3coKZdRWYHf6iUT
e4x7cgNC1fms0Fdovx8VAcTsGBJITL4/VZ6/n6V6LcVHKtuSbX9swkyWso+kHYUt
ITFTgNK9oSrCITJ/a3VZLQSP5CyNJyuhYfUj/b5sqJY63T/yJGNkaPY2EaWqmyz8
2YHv+1hYKzsGAnt1ZEgKP8uy2T9N1CNWL3PYNGu6555wiNJAIrc=
=50d/
-----END PGP SIGNATURE-----
Merge tag 'ti-k3-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.9
New Features across family / New SoCs:
- J722s SoC and board support with OSPI NOR, CPSW ethernet
- Camera capture support on mulitple J7xx SoCs, AM68, AM69 and AM62P SoCs
- Wave5 Encoder/Decoder support for J721s2, J784s4 and AM62P
Generic Cleanups/Fixes:
- Stop spliting single mbox items
- Adds MIT license along with GPL-2.0 for all TI DTS files
- Moves PCIe EP nodes in overlays
- VTM Power domain fixups for J7xx SoCs
- Conversion of mmio mux users to reg-mux where possible
- Drops unnecessary UART pinmuxes on J7xx SoCs
- MMC TAP value updates for AM64/AM62A/AM62P for improved stability
- DSS register space updates for AM65/AM62/AM62A
SoC specific Fixes/Features:
J7200:
- Adds CAN support
- New compatible for J7200 to support IO wakeup
AM62A
- HDMI Display (DSS) support
- Move to simple-bus for main_conf node
- eMMC, additional MMC/SD instance support
AM62
- move to simple-bus for main_conf node
AM654
- IOT2050-SM board support
- IOT2050 DT refractoring.
AM64
- SolidRun AM642 HummingBoard-T support and its DT overlays
- ICSSG Ethernet support and associated peripherals
Board specific fixes/Features:
- Beagle Play MDIO and USB node fixes
- TPM support on k3-am642-phyboard-electra and verdin-am62-mallow
- Phycore-am64 ADC
- PCIe + USB2.0 SERDES and PCIe + USB3.0 SERDES card support
- USB1 support on verdin-am62
* tag 'ti-k3-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (126 commits)
arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3
arm64: dts: add description for solidrun am642 som and evaluation board
dt-bindings: arm: ti: Add bindings for SolidRun AM642 HummingBoard-T
arm64: dts: ti: k3-am62p: Add Wave5 Video Encoder/Decoder Node
arm64: dts: ti: k3-j721s2-main: Add Wave5 Video Encoder/Decoder Node
arm64: dts: ti: k3-j784s4: Add Wave5 Video Encoder/Decoder Node
arm64: dts: ti: k3-am69-sk: Add support for OSPI flash
arm64: dts: ti: k3-am69-sk: Enable CAN interfaces for AM69 SK board
arm64: dts: ti: Enable overlays for SK-AM62P
arm64: dts: ti: k3-am62p: Add nodes for CSI-RX
arm64: dts: ti: k3-am62p: Add DMASS1 for CSI
arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS
arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support
arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1
arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl
arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux
arm64: dts: ti: Add common1 register space for AM62A SoC
arm64: dts: ti: Add common1 register space for AM62x SoC
arm64: dts: ti: Add common1 register space for AM65x SoC
arm64: dts: ti: k3-am642-evm: add overlay for ICSSG1 2nd port
...
Link: https://lore.kernel.org/r/e7e984db-47b9-404a-9471-5d2ed0effe1d@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds common1 register space for AM65x SoC which is using TI's Keystone
display hardware and supporting it as described in
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
Fixes: fc539b90ed ("arm64: dts: ti: am654: Add DSS node")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20240216062426.4170528-3-devarsht@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Modify license to include dual licensing as GPL-2.0-only OR MIT
license for SoC and TI evm device tree files. This allows for Linux
kernel device tree to be used in other Operating System ecosystems
such as Zephyr or FreeBSD.
While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync
with latest SPDX conventions (GPL-2.0 is deprecated).
While at this, update the TI copyright year to sync with current year
to indicate license change (and add it at least for one file which was
missing TI copyright).
Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240122145539.194512-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add SGX GPU device entry to base AM654 dtsi file.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Message-ID: <20240109171950.31010-10-afd@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add additional reg properties for UDMA and RingAcc nodes which are
mostly used by bootloader components before Device Manager firmware
services are available, in order to setup DMA transfers.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete
and will not be functional unless they are extended.
As the attached SD/eMMC is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the SDHCI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231117163339.89952-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This matches the binding for this register region which fixes a couple
DTS check warnings.
While here trim the leading 0s from the "reg" definition.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20231117141433.9461-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING in the DT file, but
the TRM says it is level triggered.
For some reason triggering on rising edge results in double the amount
of expected interrupts, e.g. for normal page flipping test the number of
interrupts per second is 2 * fps. It is as if the IRQ triggers on both
edges. There are no other side effects to this issue than slightly
increased CPU & power consumption due to the extra interrupt.
Switching to IRQ_TYPE_LEVEL_HIGH is correct and fixes the issue, so
let's do that.
Fixes: fc539b90ed ("arm64: dts: ti: am654: Add DSS node")
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20231106-am65-dss-clk-edge-v1-1-4a959fec0e1e@ideasonboard.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://lore.kernel.org/r/20231020051937.3709871-2-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
"simple-mfd" as standalone compatible is frowned upon, so model main and
MCU NAVSS (Navigator SubSystem) nodes as simple-bus as there is really
no need for these nodes to be MFD.
Link: https://lore.kernel.org/r/20231005151302.1290363-3-vigneshr@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add register range of ringacc cfg node to all k3 SoC dtsi files. This is
normally under Device Management firmware control but some entities like
bootloader have to access directly and thus required to be present in DT.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The name "clock" is not allowed for nodes, use "clock-controller" to
remove the DTS check warning.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-3-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a
syscon compatibility.
Fixes the following dtbs_check warnings:
compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long
compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long
compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy.
Drop the duplicate and misleading ti,otap-del-sel property.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The x1-clk used by trng submodule comes directly from the system clock
after a fixed divider. It is always running and has a fixed frequency
that cannot be changed, making it uncontrollable. Hence this property
should be dropped from the rng node.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221107110607.59216-2-j-choudhary@ti.com
There are 12 general purpose timers on am65 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
timers in the MCU domain that do not have interrupts routable for Linux.
We configure the timers with the 25 MHz input clock by default as the
32.768 kHz clock may not be wired on the device. We leave the MCU domain
timers clock mux unconfigured, and mark the MCU domain timers reserved.
The MCU domain timers are likely reserved by the software for the ESM
module.
Compared to am64, the timer clocks are different on am65. And the MCU
timers are at a different IO address. Then j72 adds more timers compared
to am65 with a total of 30 timers. And the j72 clocks are different.
To avoid duplication for dtsi files, eventually we may want to consider
adding timer specific shared dtsi files with the timer clocks mapped
using SoC specific files in include/dt-bindings/clock. But let's get
am65 timers usable first.
Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221115154842.7755-3-tony@atomide.com
Compared to the earlier TI SoCs, am65 has an additional level of dedicated
multiplexing registers for the timer IO pads.
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview".
For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For the even numbered timers, the CASCADE_EN bit does not do
anything. The timer cascade input routing options are shown in TRM
"Figure 12-3632. Timers Overview". For handling beyond multiplexing, the
driver support for timer cascading should be likely be handled via the
clock framework.
Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221115154842.7755-2-tony@atomide.com
Hex numbers in addresses and sizes should be rather eight digits, not
nine. Drop leading zeros. No functional change (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221115105044.95225-1-krzysztof.kozlowski@linaro.org
McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the McASP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-12-afd@ti.com
Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-11-afd@ti.com
PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com
MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-8-afd@ti.com
ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information. (These and the EPWM nodes could be used to trigger internal
actions but they are not used like that currently)
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the ECAP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-6-afd@ti.com
EPWM nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the EPWM nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-5-afd@ti.com
SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the SPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-4-afd@ti.com
I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-3-afd@ti.com
UART nodes defined in the top-level AM65x SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-2-afd@ti.com
The SA2UL hardware is also used by SYSFW and OP-TEE. It should be
requested using the shared TI-SCI flags instead of the exclusive
flags or the request will fail.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com>
Link: https://lore.kernel.org/r/20220823001136.10944-3-afd@ti.com
The first TX and first two RX PSI-L threads for SA2UL are used
by SYSFW on High Security(HS) devices. Use the next available
threads to prevent resource allocation conflicts.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com>
Link: https://lore.kernel.org/r/20220823001136.10944-2-afd@ti.com
The hardware random number generator is used by OP-TEE and is access is
denied to other users with SoC level bus firewalls. Any access to this
device from Linux will result in firewall errors.
We could remove this node, but it is still valid device description,
and it is possible it could be re-enabled in the bootloader if OP-TEE
is not used. So only disable this node for now.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com>
Link: https://lore.kernel.org/r/20220823001136.10944-1-afd@ti.com
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
*dtbs_check* on
"Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml" YAML file
resulted in the following errors.
pcie@5500000: ranges: 'oneOf' conditional failed, one must be fixed:
pcie@5600000: ranges: 'oneOf' conditional failed, one must be fixed
Cleanup "ranges" property in "pcie" DT node to fix the above errors.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210915055358.19997-7-kishon@ti.com
8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there is no
need for reg-io-width or reg-shift DT properties. These properties are
not used by 8250_omap driver nor documented as part of binding document.
Therefore drop them.
This is in preparation to move omap-serial.txt to YAML format.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
