The first ISP instance on V4M has both a channel select and core
function block, describe the core region in addition to the existing cs
region. While at it update the second ISP to match the new bindings and
add the reg-names and interrupt-names property.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250423163113.2961049-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
When describing the PHYs connected to AVB1 and AVB2, mdio nodes will be
needed to describe the connections, and each mdio node will need to
contain these two properties instead. This will make the #address-cells
and #size-cells described in the base SoC include file redundant and
they will produce warnings, remove them.
In an effort to keep all three AVB nodes style consistent add an mdio
node to AVB0 already described and rename the phy node to better
describe the PHY that is connected to AVB0 before adding more PHYs.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250107160127.528933-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The usage of the R-Car V4M CSISP bindings where merged before the
bindings where approved. At that time the family fallback compatible
where not part of the bindings, add them.
Fixes: 2bb78d9fb7 ("arm64: dts: renesas: r8a779h0: Add video capture nodes")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240826144352.3026980-7-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The usage of the R-Car V4M VIN bindings where merged before the bindings
where approved. At that time the family fallback compatible was not
part of the bindings, add it.
Fixes: 2bb78d9fb7 ("arm64: dts: renesas: r8a779h0: Add video capture nodes")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240704161620.1425409-7-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add device nodes for the PWM timers on the Renesas R-Car V4M (R8A779H0)
SoC.
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
[wsa: rebased, dropped TPU part to be upstreamed seperately]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240725194906.14644-11-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The four Cortex-A76 CPU cores on R-Car V4M share their Operating
Performance Points (OPP) table, but they have independent clocks.
All cores in the cluster can switch DVFS states independently, hence
the cluster's OPP table should not have an "opp-shared" property.
Fixes: 6bd8b0bc44 ("arm64: dts: renesas: r8a779h0: Add CA76 operating points")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/4e0227ff4388485cdb1ca2855ee6df92754e756e.1718890585.git.geert+renesas@glider.be
Add the VIN, CSI-2 and CSISP related nodes found on R-Car V4M.
One thing to note is that both CSISP0 and CSISP1 are in the same power
domain, this is different from other Gen4 SoCs (R-Car V4H). The reason
for this is that R-Car V4M only has one ISP core which is connected to
CSISP0 while R-Car V4H has two ISP cores, one connected to each CSISP.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20240527134129.1695450-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add device nodes for the remaining High Speed Serial Communication
Interfaces with FIFO (HSCIF) on the Renesas R-Car V4M (R8A779H0) SoC,
including DMA support and the optional external clock source used by
HSCIF2.
Based on a patch in the BSP by Nghia Nguyen.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b39f081db01fde2d1bf83a193f25b295cfeb002d.1709741303.git.geert+renesas@glider.be
Add device nodes for the Thermal Sensor/Chip Internal Voltage
Monitor/Core Voltage Monitor (THS/CIVM/CVM) and the various thermal
zones on the Renesas R-Car V4M (R8A779H0) SoC.
Add support for 2 TSC nodes of thermal.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/d1f07c77943912145583d8916ba3ca65d143b1b1.1709722573.git.geert+renesas@glider.be
