Add DT entries for the sm8550 iris decoder.
Since the firmware is required to be signed, only enable
on Qualcomm development boards where the firmware is
publicly distributed.
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250509-topic-sm8x50-upstream-iris-8550-dt-v4-1-22ced9179da3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add appropriate mappings of Soundwire ports of WSA8845 speaker. This
solves second (south) speaker sound distortions when playing audio.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240627122015.30945-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
OTG is default usb dr_mode, so this property can be removed.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20240531090422.158813-3-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The usb-role-switch is SM8550 SoC property, so move it from board dts
to SM8550 SoC dtsi.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240531090422.158813-2-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The orientation-switch of the USB+DP QMP PHY is not a property of the
board, it is a design property of the QMP PHY itself. Move the property
from board DTS to SoC DTSI.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-8-87c341b55cdf@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Move the graph connection between USB host, USB SS PHY and DP port to
the SoC dtsi file. They are linked in hardware in this way.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-4-87c341b55cdf@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Starting from SM8550, the TX ADC input soundwire port is offset by 1,
and uses the new SWR_INPUTx input ports, so replace the legacy
SWR_ADCx routes for SWR_INPUT0 & SWR_INPUT1 following the correct
TX Soundwire port mapping.
Add some comments on the routing for clarity.
Fixes: b5e25ded27 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240201-topic-sm8550-hdk8550-audio-fix-v1-1-aa526c9c91d5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
