A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the
opp-supported-hw appropriately.
Note that fuseval 0xac is referred to as speedbin 1 downstream, but
that was already in use upstream, so 2 was chosen instead.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230926-topic-a643-v2-4-06fa3d899c0a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
mark the GPU one as well.
Fixes: 96c471970b ("arm64: dts: qcom: sc7280: Add gpu support")
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230926-topic-a643-v2-3-06fa3d899c0a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will hang the board.
The current settings are functionally identical, *but* due to what is
likely hardcoded security policies, the secure firmware rejects them,
resulting in the board hanging. To avoid that, alter the settings such
that SID 0 and 1 are described separately.
Fixes: 96c471970b ("arm64: dts: qcom: sc7280: Add gpu support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230926-topic-a643-v2-2-06fa3d899c0a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
Describe that and make sure it doesn't interfere with Chrome devices.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230926-topic-a643-v2-1-06fa3d899c0a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
Fixes: 0e51f883da ("arm64: dts: qcom: sc7280: Add APSS watchdog node")
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20231106144335.v2.2.I11f77956d2492c88aca0ef5462123f225caf4fb4@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one.
Failing to provide it may result in register accesses failing and that's
never good.
Add the missing path.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231125-topic-rb1_feat-v3-7-4cbb567743bb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the CCI busses found on sc7280 and their pinctrl states.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20231002-sc7280-cci-v2-2-9333fda4612a@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the USB3+DP Combo QMP PHY port subnodes to facilitate the
description of the connection between the hardware blocks.
Put it in the SoC DTSI to avoid duplication in the device DTs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230929-sc7280-qmpphy-ports-v2-1-aae7e9c286b0@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The sc7280 SoC has a True Random Number Generator, add the node with
the correct compatible set.
Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Link: https://lore.kernel.org/r/20231015193901.2344590-5-quic_omprsing@quicinc.com
[bjorn: Padded address to 8 digits, moved hunk to maintain sort order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
With the standard Qualcomm TrustZone setup, components such as lpasscc,
pdc_reset and watchdog shouldn't be touched by Linux. Mark them with
the status 'reserved' and reenable them in the chrome-common dtsi.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-1-14bb7cedadf5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Qualcomm Embedded USB Debugger (EUD) second port should point to Type-C
USB connector. Such connector was defined directly in root node of
sc7280.dtsi which is clearly wrong. SC7280 is a chip, so physically it
does not have USB Type-C port. The connector is usually accessible
through some USB switch or controller.
Doug Anderson said that he wasn't ever able to use EUD on Herobrine
boards, probably because of invalid or missing DTS description - DTS is
saying EUD is on usb_2 node, which is connected to a USB Hub, not to the
Type-C port.
Correct the EUD/USB connector topology by removing the top-level fake
USB connector and EUD port pointing to it, and disabling the incomplete
EUD device node.
This fixes also dtbs_check warnings:
sc7280-herobrine-crd.dtb: connector: ports:port@0: 'reg' is a required property
Link: https://lore.kernel.org/all/CAD=FV=Xt26=rBf99mzkAuwwtb2f-jnKtnHaEhXnthz0a5zke4Q@mail.gmail.com/
Fixes: 9ee402ccfe ("arm64: dts: qcom: sc7280: Fix EUD dt node syntax")
Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Cc: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20230820075626.22600-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Since we have those defines available in a header, let's use them
everywhere where qcom,vmid property is used.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230818-qcom-vmid-defines-v1-1-45b610c96b13@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Hook up the interrupts that signal the Limits Management Hardware has
started some sort of throttling action.
Fixes: 7dbd121a2c ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-7280_lmhirq-v1-1-c262b6a25c8f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add power-domains for cpuidle states to use psci os-initiated idle states.
Cc: devicetree@vger.kernel.org
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Link: https://lore.kernel.org/r/20230703085555.30285-4-quic_mkshah@quicinc.com
[bjorn: Corrected psci child node names to match binding]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSdmeUACgkQYKtH/8kJ
UieI5A//bxZXA54htEPXN5V1oIgC4JB4UYkf8fAvtyK4tdaImMn4OTwLD8/sw18X
LQHf1VOLGsGJyNCQ+cUoaBnysr2CXqL/9dA/ARTalqnrKMN/OQjt2wg62n1Ss9Pv
XRlxJABGxAokTO/SuPtOIakSkzwDkuAkIFKfmrNQGcT95XkJXJk3FlMRr84310UG
sl6jP2XFSiLSYm958MMNt+DMhxRmKuyT9gos24KGsb83lZSm9DC2hYimkjd1KF5P
CKeShWeoGoJe+YhnJx6dsDSqVgp1DFLZF1G0auSwjs9rCAKnCDMlz+T2bEzviVDh
XONBNmnOGwPRiBI+1WdzX+pZqMMWINmhIObuODV4ANCSlX3KlSaC2rropEimlW9S
CefvYJ+i7v/BQgMLhKlft0RHhsPU7Pfhfq4PWxaIMAOWA6ZaVczMCpgeUupHIwIQ
lWXZZDlqmTL6SCgkOhEtdP2GGec7YSroq7sscinBaQs1f5pfoW83CNn46gZ9Jh8S
RnXp/+vZ7+RFc15Y0VM82F6a7WN/n0BAqKmqwceDrCpf6ILrBc1lA7NhEvd80wbB
IMg8QNqIzZ9aTOoZmB/1wAXaLClKCE3poTF+Wkd5szN7qe+hKAe1M4w5XvNUO/i/
d0/X5KNA2ykuUxRMdd4lG54VsTJdDCVNaNeaEqasv9JCBBfvuwI=
=X/KE
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
Just like for sc7180 devices using the Chrome bootflow (AKA trogdor
and IDP), sc7280 devices using the Chrome bootflow also need their
firmware marked dma-coherent. On sc7280 this wasn't causing WiFi to
fail to startup, since WiFi works differently there. However, on
sc7280 devices we were still getting the message at bootup after
commit 7bd6680b47 ("Revert "Revert "arm64: dma: Drop cache
invalidation from arch_dma_prep_coherent()"""):
qcom_scm firmware:scm: Assign memory protection call failed -22
qcom_rmtfs_mem 9c900000.memory: assign memory failed
qcom_rmtfs_mem: probe of 9c900000.memory failed with error -22
We should mark SCM properly just like we did for trogdor.
Fixes: 7bd6680b47 ("Revert "Revert "arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()""")
Fixes: 7a1f4e7f74 ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20230616081440.v2.4.I21dc14a63327bf81c6bb58fe8ed91dbdc9849ee2@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Currently in board files MDSS and DSI nodes stay apart, because labels
for DSI nodes do not have the mdss_ prefix. It was found that grouping
all display-related notes is more useful.
To keep all display-related nodes close in the board files, change DSI
node labels from dsi_* to mdss_dsi_*.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230531011623.3808538-9-dmitry.baryshkov@linaro.org
MDSS and all its subdevices are useless without DPU/MDP, so disabling
MDP doesn't make any sense. Remove explicit disabling of the DPU device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230531011623.3808538-2-dmitry.baryshkov@linaro.org
As noted by Konrad while reviewing [1], fix the EUD and DWC3
node syntax in sc7280 dtsi file.
While at it also fix the errors reported by '$ make dtbs_check'
for the EUD node:
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dtb: eud@88e0000: ports:
'oneOf' conditional failed, one must be fixed:
'port' is a required property
'#address-cells' is a required property
'#size-cells' is a required property
From schema: Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
[1]. https://lore.kernel.org/linux-arm-msm/20221231131945.3286639-1-bhupesh.sharma@linaro.org
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230502093959.1258889-2-bhupesh.sharma@linaro.org
Add required cache-level and cache-unified properties to fix warnings
like:
qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
Fix the following schema warning:
gic-its@17a40000: False schema does not allow {'compatible':
['arm,gic-v3-its'], 'msi-controller': True, '#msi-cells': [[1]],
'reg': [[0, 396623872, 0, 131072]], 'status': ['disabled']}
And reorder the properties to be more in order with all other nodes.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-4-6efb4196f51f@linaro.org
Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix
trogdor qspi pin config")), we should adjust the qspi pin config for
sc7280.
I won't re-describe all the research/arguments in the sc7180 patch
here, but there are a few differences for sc7280 worth noting:
1. On herobrine the SPI flash (qspi) is wired up differently on the
board. Rather than Cr50 and the AP being wired directly together,
there's actually a mux that will _either_ connect the AP to the
flash or Cr50 to the flash. This means that the internal pulls on
Cr50 don't affect us and we should enable our own pulldowns.
2. On herobrine, EEs added an external pulldown on the MISO line. The
argument in the schematic said that we added it (but not one on
MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and
CLK. ...though, as per #1, those Cr50 pulldowns would only affect
the line when the mux was swung to Cr50.
The ironic result of #1 and #2 is that the external pulldowns on
CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on
trogdor.
3. While I still don't have the actual exact schematics for all
variants of IDP/CRD that were produced, I have some reference
schematics that give me a belief of how the qspi is hooked up
there. From this, I'm fairly certain that all of the older variants
of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe
through a direct connect to Cr50) or have no pull (in other words,
they don't have a pullup). I'll go ahead and enable internal
pulldowns on all the lines since that won't hurt to double-pull if
there's an external pulldown and it's nice to have a pulldown if
there's nothing external. Note that this only affects _older_
CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin
device trees).
4. I didn't find the same strange "auto-switch-to-keeper" at suspend
when probing on sc7280. Whatever pulls (or lack thereof) I left at
suspend time seemed to persist into suspend.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes: 7720ea001b ("arm64: dts: qcom: sc7280: Add QSPI node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.
But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.
On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.
So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
Use the correct fallback compatible for the BWMONv4 with merged global and
monitor register spaces.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org
Nodes with unit addresses must have also 'reg' property:
sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property
Fixes: 0b05997909 ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
While at it, let's also fix the size of the llcc_broadcast_base to cover
the whole region.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.
So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org
If the controller is not marked as cache coherent, then kernel will
try to ensure coherency during dma-ops and that may cause data corruption.
So, mark the PCIe node as dma-coherent as the devices on PCIe bus are
cache coherent.
Cc: stable@vger.kernel.org
Fixes: 92e0ee9f83 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related node")
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1677584952-17496-1-git-send-email-quic_krichai@quicinc.com
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1672163103-31254-2-git-send-email-quic_khsieh@quicinc.com
The Always On Subsystem (AOSS) QMP is not a power domain controller
since commit 1357804562 ("arm64: dts: qcom: sc7180: Use QMP property
to control load state") and few others. In fact, it was never a power
domain controller but rather control of power state of remote
processors. This power state control is now handled differently, thus
the AOSS QMP nodes do not have power-domain-cells:
sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property
From schema: Documentation/devicetree/bindings/power/power-domain.yaml
AOSS QMP is an interface to the actuall AOSS subsystem responsible for
some of power management functions, thus let's call the nodes as
"power-management".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org
The SPMI bus uses two address cells and zero size cells (second reg
entry - SPMI_USID - is not the size):
spmi@c440000: #address-cells:0:0: 2 was expected
Fixes: 14abf8dfe3 ("arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213101921.47924-2-krzysztof.kozlowski@linaro.org
'arm,kryo' is not documented and is not an Arm Ltd thing either as that
is Qualcomm branding. The correct compatible is 'qcom,kryo'.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207211327.2848665-1-robh@kernel.org
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7280 against the yaml documentation.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-15-bryan.odonoghue@linaro.org
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).
To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
The SC7180 MPSS/MSS remote processor can be brought to life using two
different bindings:
1. qcom,sc7280-mpss-pas - currently used in DTSI
2. qcom,sc7280-mss-pil
Move the properties related to qcom,sc7180-mss-pil (qcom,halt-regs,
qcom,ext-regs, qcom,qaccept-regs, resets and additional clocks) to
specific board using the PIL, to silence DT schema warnings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221124184333.133911-5-krzysztof.kozlowski@linaro.org
Remove unused and redundant sleep pin control entries as they are
not referenced anywhere in sc7280 based platform's device tree variants.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reported-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1668591184-21099-1-git-send-email-quic_srivasam@quicinc.com
Update all references to OSM or EPSS L3 compatibles, to include the
generic compatible, as defined by the updated binding.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-7-quic_bjorande@quicinc.com
Use SM6350 as fallback for GPI DMA, to indicate devices are compatible
and that drivers can bind with only one compatible.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018230352.1238479-4-krzysztof.kozlowski@linaro.org
DT schema expects LPASS pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927153429.55365-3-krzysztof.kozlowski@linaro.org
The LPASS pin-controller is not a clock provider:
qcom/sc7280-herobrine-herobrine-r1.dtb: pinctrl@33c0000: '#clock-cells' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927153429.55365-2-krzysztof.kozlowski@linaro.org
The bindings require a SoC-specific compatible to be used next to
qcom,cpufreq-epss. Add it to make dtbs_check happy.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016090035.565350-2-luca@z3ntu.xyz
phy-names has been marked deprecated. Remove it from the sc7280 DSI
controller block.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220907000105.786265-8-bryan.odonoghue@linaro.org
qup-i2c devices on sc7280 are clocked with a fixed clock (19.2 MHz)
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'CX' to satisfy the 19.2 Mhz clock frequency
requirement.
Use 'required-opps' to pass this information from
device tree, and also add the power-domains property to specify
the CX power-domain.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927104233.29376-1-quic_rjendra@quicinc.com
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
I already tried to do this in commit d801357a05 ("arm64: dts: qcom:
sc7280: align TLMM pin configuration with DT schema") and I missed the
fact that these nodes were not part of "state" node. Bindings did not
catch these errors due to its own issues.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220930192954.242546-5-krzysztof.kozlowski@linaro.org
Most of the changes fall into one of three categories: adding support
for additional devices on existing machines, cleaning up issues found
by the ongoing conversion to machine-readable bindings, and addressing
minor mistakes in the existing DT data.
Across SoC vendors, Qualcomm and Freescale stick out as getting the most
updates, which corresponds to their dominance in the mobile phone and
embedded industrial markets, respectively.
There are 636 non-merge changeset in this branch, which is a little
lower than most times, but more importantly we only add 36 machine
files, which is about half of what we had the past few releases.
Eight new SoCs are added, but all of them are variations of already
supported SoC families, and most of them come with one reference board
design from the SoC vendor:
- Mediatek MT8186 is a Chromebook/Tablet type SoC, similar to the
MT65xx series of phone SoCs, with two Cortex-A76 and six Cortex-A55
cores.
- TI AM62A is another member of the K3 family with Cortex-A53 cores,
this one is targetted at Video/Vision processing for industrial
and automotive applications.
- NXP i.MX8DXL is another chip for this market in the ever-growing
i.MX8 family, this one again with two Cortex-A35 cores.
- Renesas R-Car H3Ne-1.7G (R8A779MB) and R-Car V3H2 (R8A77980A) are
minor updates of R8A77951 and R8A77980, respectively.
- Qualcomm IPQ8064-v2.0, IPQ8062 and IPQ8065 are all variants of the
IPQ8064 chip, with minimally different features.
The AMD Pensando Elba and Apple M1 Ultra SoC support was getting close
this time, but in the end did not make the cut.
The new machines based on existing SoC support are fairly uneventful:
- Sony Xperia 1 IV is a fairly recent phone based on Qualcomm
Snapdragon 8 Gen 1.
- Three Samsung phones based on Snapdragon 410: Galaxy E5, E7 and
Grand Max. These are added for both 32-bit and 64-bit kernels,
as they originally shipped running 32-bit code.
- Two new servers using AST2600 BMCs: AMD DaytonaX and Ampere
Mt. Mitchell
- Three new machines based on Rockchips RK3399 and RK3566:
Anberic RG353P and RG503, Pine64 Pinephone Pro, Open AI Lab
- Multiple NXP i.MX6/i.MX8 based boards: Kontron SL/BL i.MX8MM OSM-S,
i.MX8MM Gateworks GW7904, MSC SM2S-IMX8PLUS SoM and carrier board
- Two development boards in the Microchip AT91 family:
SAMA5D3-EDS and lan966x-pcb8290.
- Minor variants of existing boards using Amlogic, Broadcom, Marvell,
Rockchips, Freescale Layerscape and Socionext Uniphier SoCs.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmM+jwsACgkQmmx57+YA
GNnqJg//dgGHQ+dpmxvTHUAx/2WSojAyC7pXPuSoNzAiVDF+95ARM7as+5GtaeU7
me8fIw/EXQiVeEbxRPVhmGLZy0uXOhyKIQO4o58dd5YSalngI6Q7t8YFaiLCaHoF
cL7m17nk88sYOzTtSCjfnCPX8KSB7JmElsoWme3PzYhnildEmeBYfiqyqRsGP8KI
pLOec8GXfwDcnaLvBYT6EO/pAO1lZgp531spVacv4brJtQGFRbm4VuvzyFqE2b7g
0PxkRMXAE2ohrw6jAIeN2zp8BgFNPlMnuZF2cp330aX5urICk8nCo+GFAM1bK8e6
0mnKFaXEsRIphxyja8rs9B/pz4Qal2OlC1lGoeQI+QuzYEM5vOroe0EQKw0OLIyQ
YUslu4CnQgEeM9FVsm1cTYlPPf6geU8Y9vju4VwyDtgD270+5vOqMpTpiC1k4tJI
JlaZdNhp5+Cdz3W+qssrQfOP9tkQmcWNZxJQJxpy41VR+BrGoCweGZa5NifPYO7m
AwqisfppTodtF/m6XuHiQg+vDrJXPs/Ydv8vRfTeWA4/EuadewYwBhRpSKEZX7N8
HuaasPMp9rSoDvuz+kKnKFZfHuTqruwt/qnCduAk5N91z1BJD5wXtvD3zUXEwy1d
hPcDJl8M3xfgLF1t38r6srNDt/MupafaDifNAqG6QRZMr8PqvnE=
=xPfV
-----END PGP SIGNATURE-----
Merge tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"Most of the changes fall into one of three categories: adding support
for additional devices on existing machines, cleaning up issues found
by the ongoing conversion to machine-readable bindings, and addressing
minor mistakes in the existing DT data.
Across SoC vendors, Qualcomm and Freescale stick out as getting the
most updates, which corresponds to their dominance in the mobile phone
and embedded industrial markets, respectively.
There are 636 non-merge changeset in this branch, which is a little
lower than most times, but more importantly we only add 36 machine
files, which is about half of what we had the past few releases.
Eight new SoCs are added, but all of them are variations of already
supported SoC families, and most of them come with one reference board
design from the SoC vendor:
- Mediatek MT8186 is a Chromebook/Tablet type SoC, similar to the
MT65xx series of phone SoCs, with two Cortex-A76 and six Cortex-A55
cores.
- TI AM62A is another member of the K3 family with Cortex-A53 cores,
this one is targetted at Video/Vision processing for industrial and
automotive applications.
- NXP i.MX8DXL is another chip for this market in the ever-growing
i.MX8 family, this one again with two Cortex-A35 cores.
- Renesas R-Car H3Ne-1.7G (R8A779MB) and R-Car V3H2 (R8A77980A) are
minor updates of R8A77951 and R8A77980, respectively.
- Qualcomm IPQ8064-v2.0, IPQ8062 and IPQ8065 are all variants of the
IPQ8064 chip, with minimally different features.
The AMD Pensando Elba and Apple M1 Ultra SoC support was getting close
this time, but in the end did not make the cut.
The new machines based on existing SoC support are fairly uneventful:
- Sony Xperia 1 IV is a fairly recent phone based on Qualcomm
Snapdragon 8 Gen 1.
- Three Samsung phones based on Snapdragon 410: Galaxy E5, E7 and
Grand Max. These are added for both 32-bit and 64-bit kernels, as
they originally shipped running 32-bit code.
- Two new servers using AST2600 BMCs: AMD DaytonaX and Ampere Mt.
Mitchell
- Three new machines based on Rockchips RK3399 and RK3566: Anberic
RG353P and RG503, Pine64 Pinephone Pro, Open AI Lab
- Multiple NXP i.MX6/i.MX8 based boards: Kontron SL/BL i.MX8MM OSM-S,
i.MX8MM Gateworks GW7904, MSC SM2S-IMX8PLUS SoM and carrier board
- Two development boards in the Microchip AT91 family: SAMA5D3-EDS
and lan966x-pcb8290.
- Minor variants of existing boards using Amlogic, Broadcom, Marvell,
Rockchips, Freescale Layerscape and Socionext Uniphier SoCs"
* tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (617 commits)
Revert "ARM: dts: BCM5301X: Add basic PCI controller properties"
ARM: dts: s5pv210: correct double "pins" in pinmux node
ARM: dts: exynos: fix polarity of VBUS GPIO of Origen
arm64: dts: exynos: fix polarity of "enable" line of NFC chip in TM2
arm64: dts: uniphier: Add L2 cache node
arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node
arm64: dts: uniphier: Fix opp-table node name for LD20
arm64: dts: uniphier: Add USB-device support for PXs3 reference board
arm64: dts: uniphier: Add ahci controller nodes for PXs3
arm64: dts: uniphier: Use GIC interrupt definitions
arm64: dts: uniphier: Rename gpio-hog nodes
arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
arm64: dts: uniphier: Rename pvtctl node to thermal-sensor
ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node
ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card
ARM: dts: uniphier: Add ahci controller nodes for PXs2
ARM: dts: uniphier: Add ahci controller nodes for Pro4
ARM: dts: uniphier: Use GIC interrupt definitions
ARM: dts: uniphier: Rename gpio-hog node
...
USB has a requirement to put a performance state vote on 'cx'
while active. Use 'required-opps' to pass this information from
device tree, and since all the GDSCs in GCC (including USB) are
sub-domains of cx, we also add cx as a power-domain for GCC.
Now when any of the consumers of the GDSCs (in this case USB)
votes on a perforamance state, genpd framework can identify that
the GDSC itself does not support a performance state and it
then propogates the vote to the parent, which in this case is cx.
This change would also mean that any GDSC in GCC thats left enabled
during low power state (perhaps because its marked with a
ALWAYS_ON flag) can prevent the system from entering low power
since that would prevent cx from transitioning to low power.
Ideally any consumers that would need to have their devices
(partially) powered to support wakeups should look at making the
resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead
of leaving them ALWAYS_ON.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220916103124.30581-1-quic_rjendra@quicinc.com
DT schema expects TLMM pin configuration nodes to be named with '-state'
suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-40-krzysztof.kozlowski@linaro.org
SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with
external codecs using soundwire masters. Add these nodes for sc7280 based
platforms audio use case.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1657200184-29565-2-git-send-email-quic_srivasam@quicinc.com
Correct CPU BWMON unit address to match the "reg" property.
Reported-by: Stephen Boyd <swboyd@chromium.org>
Fixes: b2f3eac1b7 ("arm64: dts: qcom: sc7280: Add cpu and llcc BWMON")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908085830.39141-1-krzysztof.kozlowski@linaro.org
Some recent changes that added new syscon nodes used misspelled node names.
Fixes: 86d7c9460e arm64: dts: qcom: sm8150: split TCSR halt regs out of mutex
Fixes: 0da6033872 arm64: dts: qcom: sdm630: split TCSR halt regs out of mutex
Fixes: 8a8531e69b arm64: dts: qcom: sdm845: split TCSR halt regs out of mutex
Fixes: d9a2214d6b arm64: dts: qcom: sc7280: split TCSR halt regs out of mutex
Fixes: ce1ac53c7f arm64: dts: qcom: sc7180: split TCSR halt regs out of mutex
Fixes: fc10cfa385 arm64: dts: qcom: msm8998: split TCSR halt regs out of mutex
Fixes: 100ce22059 arm64: dts: qcom: msm8996: split TCSR halt regs out of mutex
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220905091602.20364-1-johan+linaro@kernel.org
Add cpu and llcc BWMON nodes and their corresponding
OPP tables for sc7280 SoC.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220902043511.17130-5-quic_rjendra@quicinc.com
On the lite sku where GPU Fmax is 550Mhz, voting for a slightly higher
bandwidth at the highest gpu opp helps to improve "Manhattan offscreen"
score by 10%. Update the gpu opp table such that this is applicable only
on SKUs which has 550Mhz as GPU Fmax.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220829011035.1.Ie3564662150e038571b7e2779cac7229191cf3bf@changeid
Move the USB-controller wakeup-source property to the dwc3 glue node to
match the updated binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220802152642.2516-1-johan+linaro@kernel.org
The TCSR halt regs are next to TCSR mutex (in one address block called
TCSR_MUTEX), so before converting the TCSR mutex into device with
address space, we need to split the halt regs to its own syscon device.
This also describes more accurately the devices and their IO address
space, and allows to remove incorrect syscon compatible from TCSR mutex:
qcom/sc7280-herobrine-crd.dtb: hwlock@1f40000: compatible: ['qcom,tcsr-mutex', 'syscon'] is too long
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220819083209.50844-10-krzysztof.kozlowski@linaro.org
Only one of the USB controllers supports SuperSpeed and have an SS PHY
wakeup interrupt.
Reorder the interrupts so that they match the updated binding which
specifically has the optional interrupt last.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220715070248.19078-4-johan+linaro@kernel.org
The eDP node includes two clocks which are used by the eDP PHY rather
than eDP controller itself. Drop these clocks to remove extra difference
between eDP and DP controllers.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220710084133.30976-7-dmitry.baryshkov@linaro.org
Drop #address/#size-cells from eDP device node. For eDP the panels are
not described directly under the controller node. They are either
present under aux-bus child node, or they are declared separately (e.g.
in a /soc node).
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220710084133.30976-6-dmitry.baryshkov@linaro.org
Drop #clock-cells from DP device node. It is a leftover from the times
before splitting the deviice into controller and PHY devices. Now the
clocks are provided by the PHY, while the controller doesn't provide any
clocks.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220710084133.30976-5-dmitry.baryshkov@linaro.org
Follow the schema for the DP controller and declare 5 register regions
instead of using a single region for all the registers. Note, this
extends the dts by adding p1 region to the DP node (to be used for DP
MST).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220710084133.30976-4-dmitry.baryshkov@linaro.org
The recent commit that dropped the PCIe PHY clock index failed to update
the PCIe node reference.
Fixes: 531c738fb3 ("arm64: dts: qcom: sc7280: drop PCIe PHY clock index")
Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707064222.15717-1-johan+linaro@kernel.org
This reverts commit afcbe252e9.
The commit in question caused my sc7280-herobrine-herobrine-r1 board
not to boot anymore. This shouldn't be too surprising since the driver
is relying on the name "cqhci".
The issue seems to be that someone decided to change the names of
things when the binding moved from .txt to .yaml. We should go back to
the names that the bindings have historically specified.
For some history, see commit d3392339ca ("mmc: cqhci: Update cqhci
memory ioresource name") and commit d79100c91a ("dt-bindings: mmc:
sdhci-msm: Add CQE reg map").
Fixes: afcbe252e9 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
To ease merging of bindings and dts files, the constants were replaced
with numeric values. Change them back to defined constants.
While we are at it, fix the indentation of these clocks properties to
follow established guidelines.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706145412.1566011-2-dmitry.baryshkov@linaro.org
According to Devicetree specification, the device nodes should be
generic, reflecting the function of the device. The typical name for
memory regions is "sram".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220607171848.535128-8-krzysztof.kozlowski@linaro.org
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'reg-names' as various possible combinations
are possible for different qcom SoC dts files.
Fix the same by updating the offending 'dts' files.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-6-bhupesh.sharma@linaro.org
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'clocks' & 'clock-names' for sdhci nodes:
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:0: 'iface' was expected
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:1: 'core' was expected
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:2: 'xo' was expected
Fix the same by updating the offending 'dts' files.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.
Fix the same.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Moved non-arm64 changes to separate commit]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
The AOSS QMP bindings expect all compatibles to be followed by fallback
"qcom,aoss-qmp" because all of these are actually compatible with each
other. This fixes dtbs_check warnings like:
sm8250-hdk.dtb: power-controller@c300000: compatible: ['qcom,sm8250-aoss-qmp'] is too short
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-6-krzysztof.kozlowski@linaro.org
There's no reason the timer needs > 32-bits of address or size.
Since we using 32-bit size, we need to define ranges properly.
Fixes warnings as:
```
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected
From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
```
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz
DT schema expects names of operating points tables to start with
"opp-table":
ipq6018-cp01-c1.dtb: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$'
Use hyphens instead of underscores, fix the names to match DT schema or
remove the prefix entirely when it is not needed.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220627093250.84391-1-krzysztof.kozlowski@linaro.org
Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for the
USB core, but there are the usual "hot spots" of development activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes. It seems this driver will never
be finished given that the IP core is showing up in zillions
of new devices and each implementation decides to do something
different with it...
- uvc gadget driver updates as more devices start to use and
rely on this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCYpnZGw8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ymQhwCeLVANsQjBcL4ys4skl+1In17y28gAn3rEZ7rQ
Yv4uP9zadUqg3Cx0vjgf
=3s5s
-----END PGP SIGNATURE-----
Merge tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for
the USB core, but there are the usual "hot spots" of development
activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes.
It seems this driver will never be finished given that the IP core
is showing up in zillions of new devices and each implementation
decides to do something different with it...
- uvc gadget driver updates as more devices start to use and rely on
this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems"
* tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits)
USB: new quirk for Dell Gen 2 devices
usb: dwc3: core: Add error log when core soft reset failed
usb: dwc3: gadget: Move null pinter check to proper place
usb: hub: Simplify error and success path in port_over_current_notify
usb: cdns3: allocate TX FIFO size according to composite EP number
usb: dwc3: Fix ep0 handling when getting reset while doing control transfer
usb: Probe EHCI, OHCI controllers asynchronously
usb: isp1760: Fix out-of-bounds array access
xhci: Don't defer primary roothub registration if there is only one roothub
USB: serial: option: add Quectel BG95 modem
USB: serial: pl2303: fix type detection for odd device
xhci: Allow host runtime PM as default for Intel Alder Lake N xHCI
xhci: Remove quirk for over 10 year old evaluation hardware
xhci: prevent U2 link power state if Intel tier policy prevented U1
xhci: use generic command timer for stop endpoint commands.
usb: host: xhci-plat: omit shared hcd if either root hub has no ports
usb: host: xhci-plat: prepare operation w/o shared hcd
usb: host: xhci-plat: create shared hcd after having added main hcd
xhci: prepare for operation w/o shared hcd
xhci: factor out parts of xhci_gen_setup()
...
