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arm64: dts: qcom: sc7280: Add QSPI node

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Add QSPI DT node and qspi_opp_table for SC7280 SoC.

Move qspi_opp_table to / because SPI nodes assume
any child node is a spi device and so we can't put the
table underneath the spi controller.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-3-git-send-email-rajpat@codeaurora.org
This commit is contained in:
Roja Rani Yarubandi 2021-09-23 17:46:12 +05:30 committed by Bjorn Andersson
parent 07b2fb6046
commit 7720ea001b
1 changed files with 61 additions and 0 deletions
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61
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@ -454,6 +454,25 @@ psci {
method = "smc";
};
qspi_opp_table: qspi-opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@ -1469,6 +1488,23 @@ usb_2_dwc3: usb@8c00000 {
};
};
qspi: spi@88dc000 {
compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
interconnects = <&gem_noc MASTER_APPSS_PROC 0
&cnoc2 SLAVE_QSPI_0 0>;
interconnect-names = "qspi-config";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@ -1664,6 +1700,31 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qspi_clk: qspi-clk {
pins = "gpio14";
function = "qspi_clk";
};
qspi_cs0: qspi-cs0 {
pins = "gpio15";
function = "qspi_cs";
};
qspi_cs1: qspi-cs1 {
pins = "gpio19";
function = "qspi_cs";
};
qspi_data01: qspi-data01 {
pins = "gpio12", "gpio13";
function = "qspi_data";
};
qspi_data12: qspi-data12 {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";